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Silicon-on-insulator at ST and IBM closing gap with Intel

4/16/2012 06:54 PM EDT
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Adele.Hars
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
Adele.Hars   4/24/2012 4:57:49 PM
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As you know, Kris, major architectural choices are made years ahead of when we hear about them, and in the past the wafers had to be ready years ahead of the final choices. So that might have been a factor for Intel? And of course there's the question of where any given company put its priorities: margin, power, performance, etc. But I was a little surprised that the news I'm hearing about Intel's getting 20% less power and 20% more performance with this new architecture. Somehow I thought they'd get more. What did you think? IBM will do their FinFETs on SOI at 14nm, I understand. And they call their flavor of FD-SOI ET-SOI. To the best of my knowledge, AMD has not actually given any indication of what they'll do at 20/22nm. (And remember that 28nm was *never* on the SOI-based part of their roadmap.) So maybe the jury's still out on that one. But for sure there lots and lots of grumbling out there about yield & scaling right now. The FD (SOI) solutions (for both planar & 3D) take care of the variability problems that kill yield. Do you think that might sway a few votes?

the_floating_ gate
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
the_floating_ gate   4/18/2012 4:47:52 AM
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Mark said that they made the choice for trigate back in 2008, when it became clear that the performance benefit from the fully depleted triple-gate structure (compared to 22-nm planar) was significant enough to justify the additional effort and cost of another step-function change in process architecture. Compared with the 32-nm equivalent, the trigate gives a 37% performance increase at a lower voltage or a 50% power reduction at constant performance. Somehow Intel does this with no extra mask levels and only 2-3% additional cost (although extra litho steps are used, because of the need for double patterning). http://www.electroiq.com/blogs/chipworks_real_chips_blog/2011/09/intel-enlarges-process-lead-over-their-competition.html

krisi
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
krisi   4/17/2012 5:13:49 PM
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thank you Adele, great explanations

krisi
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
krisi   4/17/2012 4:49:28 PM
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thank you Adele, interesting blog...but as ST-E insists on advantages of fully depleted SOI over bulk CMOS it begs a question why others (I think Intel and AMd are in this camp) think the bulk CMOS is a way to go at 22nm...is it because of Fin-FET device? Kris

Adele.Hars
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
Adele.Hars   4/17/2012 4:25:24 PM
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Check out ST-Ericsson's Technology blog -- just posted today. They really spell out (with a great chart) the advantage they're getting with 28nm FDSOI -- see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/. Their conclusion: "So, over a large Vdd range (from 0.5V up to 1.3V), FD-SOI comprehensively outperforms existing bulk CMOS processes dedicated to mobile applications. This extra performance gain can be used either to increase peak performance or to operate at a lower Vdd for the same performance, saving dynamic power."

Adele.Hars
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
Adele.Hars   4/17/2012 4:18:42 PM
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Things just got even more confusion. Up to this point, all SOI (on the digital side) has been partially-depleted. Now the industry's moving to fully depleted. Fully depleted can be done on bulk or SOI. But, the only way to currently do fully depleted and keep the current planar ("2D") transistor approach is to use the ultra-thin SOI wafers. That's what STM and STE are doing at 28nm; the port to FD-SOI (as it's commonly called when it's 2D) will take their existing bulk designs to 14nm without upheaval, and they get really impressive results re: power/perf. They say it's particularly well-suited for the SOCs they're building for their target markets (smartphones, etc.) FinFETs and other multigate devices are also fully depleted, and by virtue of their verticality are referred to as 3D (not to be confused with the whole TSV 3D thing!). FinFETs were invented on SOI, then Samsung found a way to do them on bulk -- but at a price in terms of the power/perf trade-off (if you do them on bulk, you have to dope, and then you get RDF, etc). Doing FinFETs on SOI gives a big boost in terms of the power/perf advantages FinFETs promise (plus no doping). Soitec says it's also found that by using the SOI wafers for FinFETs, you save massively in terms of process steps. And they're also saying that those who opt for FinFETs on SOI should be able to cut their learning curve by about a year. Lots more good info at the SOI Consortium website. See the FD-SOI Workshop presentations -- lots of detail on both planar & FinFET on SOI.

the_floating_ gate
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
the_floating_ gate   4/17/2012 4:10:56 PM
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Looks like the article was edited and the portion about Intel's "reluctance" (without giving explaination as to why) adopting SOI was eliminated. It's good to have some one like Mark Bohr on the team BTW that's a fairly wide range "But their price is recouped from process simplifications to give a three-to-10 times overall cost reduction."

KarlFredrik
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
KarlFredrik   4/17/2012 10:44:59 AM
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It's ST-Ericsson not ST-Erikson.

CityChipMan
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
CityChipMan   4/17/2012 8:40:52 AM
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I thought AMD was the main user of SOI with Global Foundries, but is now moving away from this approach??

the_floating_ gate
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
the_floating_ gate   4/16/2012 11:58:18 PM
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I know that Varian is working with Soitec on SOI and a good portion of premium probably applies to higher cost. http://www.fabtech.org/news/_a/varian_and_soitec_to_qualify_new_high_current_implanter_for_fully_depleted_/ I suppose IBM did not learn from the gate first versus gate last debacle

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