LONDON – ARM has announced the availability of Seahawk, a Cortex-A15 processor designed as a quad-core hard macro for implementation in the 28HPM process from foundry Taiwan Semiconductor Manufacturing Co. Ltd.
The Seahawk is designed to operate at a clock frequency of up to 2-GHz and deliver in excess of 20,000-DMIPS of performance. It also represents the highest performance ARM processor hard core available to date.
The configuration includes the NEON 128-bit SIMD architecture extension to provide multimedia support and a floating point unit. There is error correction for L1 and L2 caches. There are two 32-kbyte L1 caches and 2-Mbyte L2 caches. The design supports 224 interrupts and 6 power domains, according to Hadyn Povey, director of marketing for the ARM processor division, who writes about the hard core on the ARM website.
The hard macro was developed using ARM Artisan 12-track libraries and the recently announced Processor Optimization Pack for the Cortex-A15 on TSMC 28nm HPM process.
The argument runs that even with the use of the POPs to speed up ARM SoC designs, time-to-market could be too long for some customers. For those happy to take what ARM provides by way of trade-offs the hard-macro is ready to go.
Further configuration and implementation details of Seahawk are being provided at the Cool Chips conference due to take place April 18 to 20 in Yokohama, Japan.
Boy, EETimes has gone down hill since I last checked--what could have been an interesting article, was just a rewrite of a press release (the rewrite was poorly written, too). I got better and more accurate info. by reading the press release),
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