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Intel, Micron on sub 20-nm and insatiable thirst for memory

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4/18/2012 04:51 PM EDT
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Peter Clarke
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
Peter Clarke   4/20/2012 10:36:40 AM
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Although, Intel did gain a lot of ferroelectric memory knowledge in their research with Thin Film Electronics a few years back. But I agree there is no sign they are using that knowledge directly in these NAND flash memories. The conventional wisdom is for companies to go to vertically stacked NAND memory cells thus keeping the same planar geometry (and electrons per bit) while getting greater memory denistry per die area.

cidbarca
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
cidbarca   4/20/2012 7:17:08 AM
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Thanks resistion, I think I see now. The high-k dielectric's polarization isn't used as a memory element at all. Is it correct to think of it as simply providing a capacitance threshold that's used as the limit on current flow?

resistion
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
resistion   4/20/2012 2:25:11 AM
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So far it's just floating gate with high k at 20 nm.

cidbarca
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
cidbarca   4/19/2012 7:40:36 PM
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If I'm reading this correctly, Intel/MU say they have started "volume production" of a ferroelectric NAND device; that others (such as a group from AIST, see below) have been working on similar IP but are far behind because they are focused on (a) a different ferroelectric material as compared to the gate material Intel has developed, and (b) a more complicated FinFet structure rather the "old school" planar circuit design developed by MU. see AIST work disclosed at: (2008 cell demonstration) http://www.aist.go.jp/aist_e/latest_research/2008/20080624/20080624.html (2012 64Kb cell array demonstration) http://www.nanowerk.com/news/newsid=23983.php I find this all very very very difficult to believe in view of the industry's track record of premature claims of new NV memory "production;" but most of all because Intel/MU are claiming to be able to produce this planar "Fe-NAND" device at sub 30nm lithographies currently with plans to soon drop production below the 20nm node. Such devices with even half the performance claimed for the AIST cell design would go through the current FLASH application markets like something through a goose. Has Intel/MU developed a new memory IP or just a new promotion? Have they ever submitted anything at an industry conference on such IP?

resistion
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
resistion   4/19/2012 3:19:34 PM
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So Micron is not getting on the 3D NAND train?

krisi
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re: Intel, Micron on sub 20-nm and insatiable thirst for memory
krisi   4/18/2012 11:29:46 PM
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If there is only 20 electrons difference left between two memory states there is not much hope that this technology will scale beyond 20nm process...time to employ spin instead of charge? Kris

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