LONDON – A couple of set-backs for developers of sub 20-nm manufacturing processes in recent months have accentuated the need for EUV lithography to come good and are likely to drive demand for the technology in 2014, according to Eric Meurice, CEO of lithography equipment maker ASML Holding NV (Veldhoven, The Netherlands).
ASML has been developing extreme ultra violet (EUV) lithography for many years as an eventual replacement for its own highly successful optical lithography machines, the technology currently used with multiple patternings to achieve leading-edge chip manufacturing at 28-nm and 22-nm. However, ASML's EUV systems are still below the nominal throughput specification of about 100 wafers per hour that is generally thought to be necessary to allow volume manufacturing of chips. While the use of optical lithography is just about possible at 14-nm design rules the need for triple and quadruple exposures significantly increases the cost and reduces the throughput of optical lithography at such extreme geometries.
While ASML expects to ship 11 NXE:3300B EUV litho machines in 2012 and 2013 for process development and pilot production there are two contenders to drive the ramp of EUV production at the end of 2013 and during 2014, according to Meurice.
Speaking to analysts on a conference call to discuss the company's financial results in the first quarter of 2012, Meurice said that the DRAM 1x or 1y generation, a process node just below 20-nm, was looking very complex using multipatterned optical lithography and DRAM makers seemed prepared to wait for EUV lithography to be ready for production of that node.
The other race competitor is 14-nm logic process technologies, particularly when under development at foundries, Meurice said. "The 14-nm logic node has in particular shown two major push-backs by end customers attempting to use multipatterning. They have seen two problems. One is a cost issue which is too high to justify the shrink and the second is they have seen a shrink factor limitation to 14-nm, you do not really reduce the die size as much as with EUV," he said on the conference call.
Meurice added: "The race is on to know who is going to be the first to get into [EUV] production. That will create demand in 2014, which we believe will be not too much and not too small for a company like us." Meurice said that NAND flash memory makers were not showing great interest in EUV lithography at present because they need high throughput.
When asked if the multipatterning issues at 14-nm applied to both integrated device manufacturers (IDMs) and foundries Meurice said: "At 14-nm foundries have a challenge that the IDMs would not have. The challenge is that thay have to deliver design rules which are less restrictive and they have to deliver a shrink that is very aggressive." As such the decision to go to EUV for 14-nm concerns the foundry environment more than the microprocessor environment, Meurice said.
However, timings are becoming extremely tight for some of those decisions. On the same call Meurice said ASML expects to raise the source power to 100-W, and therefore the throughput for its EUV lithography machines to 60 wafers per hour, by the end of the summer. But Meurice also said customers' EUV insertion decisions have to be frozen in the summer.
There is an underlying assumption in this discussion that the cost of an EUV tool that could meet 100WPH would actually be lower cost than a triple patterning immersion solution. Especially when you add in the potential need to regularly replace EUV masks due to defects that occur without a pellicle to protect them. What would be the reaction if after they finally get it working it costs more than multi-patterning methods?
Logic needs defect-free EUV, which means inspection tools ASML has no influence over. DRAM has billions of contacts which each require a noisier level of EUV photons, so they will require dose to increase for higher resolution. ASML has done all it could under its control, no one will fault it for giving up EUV. Unless it won its immersion orders by promising EUV.
My understanding is that Intel has already frozen their 14 nm design rules so EUV will not be Intel's litho tool of choice at 14 nm. Since the biggest ship (Intel) has already sailed and the IBM fab club and TSMC must be close behind them who does that leave? I think ASML is just now admitting what has been apparent for several months, that EUV will miss yet another major node.