PORTLAND, Ore.—The first automated software-to-chip dream came out of the closet Monday (April 23), when Algotochip Corp. (Sunnyvale, Calif.) claimed to be able to produce a system-on-chip (SoC) design from a C-code specification in just eight to 16 weeks.
"We can move your designs from algorithms to chips in as little as eight weeks," said Satish Padmanabhan CTO and founder of Algotochip, whose EDA tool directly implements digital chips from C-algorithms. "Our solution provides the appropriate RTL generated from C-ocde for SoC.
Algotochip said its technology, announced at the Globalpress Electronics Summit 2012 in Santa Cruz, Calif., generates all aspects of a solution including the software, firmware and hardware from the designers C-code and test stimulus vectors. Padmanabhan, former co-founder and chief architect at ZSP (acquired by Verisilicon in 2006), where he created the first superscalar DSP, recruited software experts from Apple and elsewhere two years ago, and today unveiled its proprietary engine that accepts as input a C-code file and outputs a Graphic Data System II (GSDII) suitable for creating SoC.
Algotochip said it had proven its methodology at half dozen customers so far, but disclosed only one: MimoOn GmbH (Duisburg, Germany) whose mimoOn mi!, a mobile PHY for LTE, has already been successfully fabricated by TSMC. Two"what if" designs were produced in 12 weeks for MimoOn, one for TSMC's 40-nanometer process and a second for its 90-nanometer process, Algotochip said. The latter of which was chosen for its final SoC due to its lower power consumption, the company said.
Algotochip starts with designers C-code (left) the generates an application-specific programmable microcontroller (top), and digital signal processor (DSP) along with a memory management unit (MMU) and input/output which implements an SoC (click on image to enlarge).
Altotochip has achieved this—the Holy Grail of SoC designers—by virtue of suite of software tools that interprets a customers' C-code without their having any knowledge of Algotochp's proprietary technology and tools. The resultant GDSII design, from which an EDA system can produce the file that goes to TSMC, and all of its intellectual property (IP) is owned completely by the customer—with no licenses required from Algotochip. If a designer wants to use a licensed core from ARM or other popular vendor, Algotochp can also accommodate on demand.
Algotochip's design flow first makes an analysis of the designers C-code from which it provides optimization suggestions for the C-code design, from which Algotochip generates a set of system specifications with options. Once the designer answers a questionnaire about their choices, Algotochip designs the base system architecture, and produces a complete SoC design including firmware and software which it then delivers to the designer in 8-to-16 weeks—from the day the C-code is delivered to Algotochip to the day the GDCII is delivered back to the designer.
Algotochip also claims its patented power-aware architecture tightly control leakage power for long battery life of mobile designs, and will also work with other implementation technologies besides SoCs, including DSPs, ASICs, ASSPs and FPGAs.