MOUNTAIN VIEW, Calif. – Next-generation 20 nm processes can support optimized versions for low power and high performance, according to an IBM expert. GlobalFoundries will decide in August whether or not it will offer such variations.
Those were just two data points from wide ranging discussions at the GSA Silicon Summit here. Separately, executives said a variety of 3-D ICs will hit the market in 2014 despite numerous challenges, and CMOS scaling is slowing down but still viable through a 7 nm node.
“Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don’t believe that,” said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. “I believe at same node you can have two [different variations],” he said in a keynote here.
Indeed, GlobalFoundries is debating whether it wants to offer high performance and low power variants of a 20 nm process it is putting in place today.
“We are still talking with lead customers to see what is the right thing to do, and there’s a lot of interest in performance and power trade-offs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries in a brief interview with EE Times.
The variations available at 20 nm may be relatively narrow and may not be economically viable, he said. Iyer of IBM said TSMC’s decision to offer one flavor of 20 nm may have been more of an economic than a technical decision.
The follow-on 14 nm process using FinFETs will open up greater opportunities for a high performance version at up to 0.9 volts and a low power variant at down to 0.6 volts, Kengeri said. In addition, the 14 nm node could offer as much as twice the typical benefits of moving to a new node.
The historic challenge of offering variations of a process is that each one requires a different set of unique and complex features added to the base process, said Iyer of IBM. “All the little features we have are like drugs, we can’t drop them without severe withdrawal symptoms,” he said.
There's room for variation at 20 nm, said Subramanian Iyer.
While scaling down exponentially to smaller and smaller sizes is the goal for engineers, if it makes no financial sense to do so, businesses would not fund that kind of development. Innovation here depends a lot on the profitability of making smaller and smaller chips. No one would want to spend so much resources to make a smaller chip if it doesn't have potential to make more money for chip makers.
Mary - http://www.jensenmarinedirect.com
Rick, if you or anyone else wants to better understand fully depleted (FD) planar or FinFET (3D) SOI (all very different from the partially depleted SOI IBM et al have long been using for high perf), lots of good info at www.soiconsortium.org. Also recommend an excellent white paper there posted by ST explaining their choice of FD-SOI for 28nm SOCs.
And ST-Ericsson's got a really interesting blog going on about it it (they tape out the new NovaThor smartphone SOC on 28nm FD-SOI in Q3) -- see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/ . He says that FD-SOI at nominal voltages gives similar peak performance to HP processes and more than 35% performance improvement compared to LP at same Vdd; and it does far better on leakage & variability.
But I too would really like to hear more from anyone who was at the GSA Summit.
@rick.merritt: looks like you left before the GSA 3DIC Workgroup meeting that day where some interesting points were made (couple from myself!). While it is true that some companies (Samsung, Micron) are building 3DIC (TSV-enabled) memory products, the ecosystem challenge still remains as are the standards. There will be more discussions on these two at the upcoming GSA meetings.
I agree. I think this or a separate article needs to present the SOI portions of this GSA Silicon Summit. I did learn a lot about the merits of FD-SOI specially at low voltages. Items like ST is using this technology for 28 and 20nm were relevant. The numbers were actually impressive.
Frankly, yes the event was something of an SOI love fest. But it's a topic that has been around for years and one I (also frankly) don't have much perspective on.
So I focused on what seemed like the top issues I understand and are significant to a broad readership: The industry is moving to 3-D ICs, there is a debate about 20nm and the outlook for CMOS is hard but OK to 7 nm.
I'll let those interested in marketing SOI take out ads ;-)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.