LONDON – Reverse engineering and analysis consultancy Chipworks Inc. has posted microscope cross-sections of parts of the 22-nm Ivy Bridge processor from Intel that has revealed that the FinFETs, which Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, in cross-section.
The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.
The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.
Gold Standard Simulations Ltd. (Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its website: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.
Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks
blog (above) with the Garand simulation domain of Gold Standard Simulations.
GSS's simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel
transistor and an equivalent rectangular-fin transistor. "Clearly the
rectangular fin has better short channel effects. Still, the million-dollar
question is if the almost-triangular shape is on-purpose design, or is this
what bulk FinFET technology can achieve in terms of the fin etching?"
The comparisons between dimensionally comparable rectangular and
trapezoidal FinFETs are not markedly different but as GSS had no
knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper
below the fin in the shallow trench isolation (STI) region. "Clearly
FinFETs are more complicated devices in terms of understanding and
visualization compared to the old bulk MOSFETs," GSS concluded.
I suspect that the "triangle" shape represents some compromise between what is simple and reproducible to fabricate with regards to high volume manufacturing considerations, and what is the ideal shape from from an electrical standpoint. It is also a more mechanically robust shape for a relatively high aspect ratio structure (less likely to break due to vibration, etc.).
Avoiding sharp corners is always a good idea in silicon manufacturing due to electric field crowding in device operation...and even if you wanted sharp fin it would be difficult to make it always equally sharp hence yeild hit...I suspect 2012 pics were of the marketing types...Kris
Simplest way to put it, rectangles have one more corner than triangles. Besides process variation, corners tend to have leakage current affecting off-stage performance, such as Vt and Ioff. In addition, the equivalent width of the FinFET may be easier to scale and control in triangular shape than in rectangular shape. It will be interesting to see NMOS vs PMOS with various width and how the width scaling is done.
iniewski has it right on one aspect.
Avoiding sharp corners is plausible advantage.
The second aspect I suspect is the ability to measure sidewall roughness without sidewall afm - atomic force microscopy that taps laterally ( the old IBM AFM that was a poor machine ). Here with sloped sidewalls, a topview high resolution SEM electron microscope images sidewalls usefully, and a comventional AFM topview tapping more trivially gets the needed "sidewall" roughness quantitaitvely measured with little difficulty versus the challenging vertical 90deg sidewall. And manufacturing metrology ease and accuracy of roughness here, which is a critical device parameter, since the surface is ETCHED ( worst thing you normally might do for a desired atomically smooth surface )...
Hence I suspect nano- metrology aspects are the driver ( this being a process engineer's perspective, not theoretical in the slightest )
Perhaps it was intentional to flood the media with sketches& even SEMs of rt. angled fins so that the pretenders and knock off artists would be misled for a while. But the important thing is that the power consumption for Ivy Bridge ( 22 nm, FinFET ) is NOT yet significantly less than Sandy Bridge to get a foot in the door at the SoC for SmartPhones house.
Corner leakage is usually a problem, but so is reproducability and control. It is difficult to know from so little data, how much of this triangle approach is for leakage vs. process control (yield). If the power levels don't give a dividend it will all be for naught.
Don't these sloped fins cause a lot of variation?
The device channel orientation is random vs 110 for ideal finfet and 100 for planar (mobility and many sources of variation)
Fin thickness depends on sidewall slope....and fin thickness sets my leakage and device threshold voltage, right?
I have bee puzzled why everyone claims trigate lowers standby leakage BUT I don't see any improvement in standby power at the chip level for intels 22nm ivy bridge??
Could this be the reasons leakage improvement does not match expectation for "ideal trigate".
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