LONDON – Reverse engineering and analysis consultancy Chipworks Inc. has posted microscope cross-sections of parts of the 22-nm Ivy Bridge processor from Intel that has revealed that the FinFETs, which Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, in cross-section.
The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.
The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.
Gold Standard Simulations Ltd. (Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its website: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.
Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks
blog (above) with the Garand simulation domain of Gold Standard Simulations.
GSS's simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel
transistor and an equivalent rectangular-fin transistor. "Clearly the
rectangular fin has better short channel effects. Still, the million-dollar
question is if the almost-triangular shape is on-purpose design, or is this
what bulk FinFET technology can achieve in terms of the fin etching?"
The comparisons between dimensionally comparable rectangular and
trapezoidal FinFETs are not markedly different but as GSS had no
knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper
below the fin in the shallow trench isolation (STI) region. "Clearly
FinFETs are more complicated devices in terms of understanding and
visualization compared to the old bulk MOSFETs," GSS concluded.
Finfets should provide power/perforamance advantage. Intel probably set their process to fit within a given power budget -- get as much performance as possible within that limit.
For example, lower transistor threshold voltages -- faster & more leakage. Intel would set process knobs like this to get as much performance as possible without blowing power limit.
For low power parts, Intel could set these knobs differently.
Agree. Lower transistor threshold voltage results in faster but leaker part. If intel was taking all trigate leakage improvement and targeting performance, I don't understand why performance and or frequency is about the same? Ivy bridge frequency bins are only ~100Mhz higher vs 32nm sandy bridge. Clock frequency of 3.4 vs 3.5Ghz or performance benchmarking is less than I was expecting.
I still wonder if this trigate is really going to give intel a competitive advantage in mobile? Or is intel marketing misdirecting from their own short comings. Stock analysts in my opinion are often wrong but when I look at the data I think Gus Richards might be right.
Trigate has higher processing cost and extra design restriction (increases cost via larger die area). I looked at designing my I/O block with finfet (foundries name for trigate). Layout was larger (higher cost) and at block level my power was higher.
It will be interesting to watch if intel can make a better cell phone or tablet chip. But they better hurry since 28nm chips with improved power are ramping fast.
the other driver for a tapered triangular Silicon FIN is to avoid / minimize ion implant shadowing in the source drain / graded drain ion implants ( if implanted ). A vertical FIN sidewall would likely introduce asymmetric and wafer rotational dependence on Source Drain offset with respect to the edge of the FIN channel. Another process latitude driver for FIN triangular shape.... ( ie not merely metrology )
I spoke to my go to fab guy
He said the fin shape results from a gross electrical compromise to clear spacer off fin (required for the si and SiGe fin epitaxy). Vertical fins create better electrical uniformity and performance. But its very difficult to clear spacer off a vertical fin. He does not think this fin shape will work for foundry SOC chips. Too much electrical variation and leakage
Makes sense. Consistent with
Intels 22nm chip voltage was raised to slightly greater than 1V vs foundry mobile parts that run 0.85 to 0.9V
b) intel 22nm parts having high leakage / leakage power.
I hope GSS publishes more on this topic. Very good work and helpful.
The original explanation from Intel, why back when, was that the gate wrapped around three-sides of the rectangular cross-section fin.
If the fin is trapezoidal then tri-gate name is still ok, but if that fin is triangular in cross-section then perhaps Intel should go with bi-gate?
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