JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, has published the JESD209-3 LPDDR3 Low Power Memory Device Standard.
The standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smart phones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its groundbreaking predecessor, LPDDR2.
LPDDR3 achieves a data rate of 1600 Mbps (versus 1066 Mbps for LPDDR2) through the addition of new features, including:
- Write-leveling and CA training: These features allow the memory controller to compensate for signal skew, ensuring that requirements for data input setup and hold timing, as well as command and address input timing, are met while operating at the industry’s fastest input bus speeds
- On-die termination (ODT): This optional feature enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count
As with LPDDR2, LPDDR3 supports both package-on-package and discrete packaging types in order to meet the requirements of a wide array of mobile devices, offering designers the ability to select the options that best meet the needs of their product. LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management.
“LPDDR3 builds on the revolutionary LPDDR2 standard, which paved the way for an entire generation of high-performance, low-power mobile devices,” said Mian Quddus, JEDEC Board of Directors Chairman. “Now with LPDDR3, JEDEC has taken the standard to a new level, and we are pleased to offer a solution for the performance demands of a new generation of mobile products.”
“To help address the dramatic rise in data-intensive apps and the resulting demands on device memory, JEDEC LPDDR3 is designed to focus on higher bandwidth requirements for device processors and graphic units,” added Hung Vuong, Chairman of JC-42.6. “LPDDR3 represents countless hours of collaboration within the JC-42.6 Subcommittee, and was developed rapidly in order to meet the mobile industry’s bandwidth requirements.”
Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC website
.This article originally appeared on EE Times Europe.