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IMEC looks at variability issue beyond 10 nm

6/1/2012 09:10 PM EDT
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resistion
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re: IMEC looks at variability issue beyond 10 nm
resistion   6/2/2012 1:41:57 AM
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The move to sidewall gate oxide actually presented an extra scaling impediment.

goafrit
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re: IMEC looks at variability issue beyond 10 nm
goafrit   6/3/2012 11:10:52 AM
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I am concerned that companies are seeing this process migration as a strong competitive weapon. I do not think it makes a lot of difference if you are not Intel making these billion transistor microprocessors.

yalanand
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re: IMEC looks at variability issue beyond 10 nm
yalanand   6/3/2012 1:02:18 PM
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Thanks for sharing the Variability challenges slide. This beautifully explains the challenges we face at different nodes. No doubt sub 10nm node we will face lot of issues but am sure with the latest technology available we will eventually break the 10nm node barrier.

Yog-Sothoth
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re: IMEC looks at variability issue beyond 10 nm
Yog-Sothoth   6/3/2012 5:07:54 PM
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These people who say 'Moores law will continue' probably never studied physics, perhaps even basic maths. Silicon has a lattice constant of 5.43095 anstroms. 1 angstrom = 0.1nm i.e. the spacing between crystalline silicon atoms is about 0.5nm. So once you get below 10nm, there aren't that many atoms in your channel. At 7nm you've got roughly 14. Now, do you think you can make devices that operate in bulk mode when you're down to atomic scale (assuming you can pattern stuff similarly small)?

Chipguy1
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re: IMEC looks at variability issue beyond 10 nm
Chipguy1   6/5/2012 8:09:30 PM
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Correct. You may even be able to make the transistor smaller (.i.e. "7nm roughly 14 atoms") but the smaller transistor tends not to be better or even if the mean values of the transistor is "better" (improved performance or power) a product made with a billions of the transistors will not improve or will improve less due to variability ( i.e. some transistors have 13 atoms or the worse billion transistor might only have 5 atoms). I think we are seeing the early signs of Moore's Law slowing already and your logic correct. For the most advanced node intels 22nm (where parts of the silicon fin are only ~7nm thick), , I do think at the transistor level a single CMOS inverter (2 transistor )improves power ~50% per intel's data ....but ivy bridge product shows much less if any power improvement. For example, Ivy bridge shows worse power. Actual number depends where you benchmark the part. One benchmark case is over clocking where the worse power leads to higher chip temperature.

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