SAN FRANCISCO – Globalfoundries reported progress ramping four flavors of its 28nm process and early work qualifying its 20 nm process and gathering 3-D IC partners at the Design Automation Conference here. Its larger competitor TSMC also announced progress in the same three areas, including the tape out of a test 3-D IC chip working in collaboration with Cadence Design Systems.
“We just passed shipment of 400,000 32/28 nm high-k metal gate wafers and we’re ramping rapidly,” said Mojy Curtis Chian, senior vice president of design enablement at Gobalfoundries in an interview with EE Times at DAC. “We have proved gate first works, is high yielding and economical,” he said.
The company has four flavors of its 28 nm process in various levels of readiness at its Fab 8 in New York. The low power version for mobile chips and a low cost polysilicon version without high-k metal gates are ready. First tapeouts are in progress for a high performance variant for networking and storage chips, and a version between the high performance and low power variants is in joint development with Samsung.
Globalfoundries estimates only about ten percent of its total 90,000 wafers/month capacity will come from its Fab 8 by the end of the year. But 12 months later that could expand to nearly a third of about 180,000 wafers/month as the foundry spends an estimated $3 billion in capital equipment this year.
Meanwhile at least three companies are about to participate in Globalfoundries’ first multi-process wafer to qualify its 20 nm process also in New York. The company expects to run several of the shuttles this year so it can start 20 nm production early in 2013 with tested third-party IP where needed.
Double patterning is required for any features with a pitch below 78 nm in the process. Designs will vary greatly from requiring double patterning on only one to as many as six layers.
“Typically in networking and high performance graphics you will use higher numbers of metal layers and higher numbers of minimum size features,” Chian said.
The extra processing and masks costs will slow broad adoption of the process. But leading-edge chip makers are aggressively pursuing the technology and broader adoption will come eventually, Chian said.
“Overall the life of 28nm will be longer [than the typical node] so the two technologies will coexist,” he said.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.