LONDON Ė Chip vendor STMicroelectronics NV (Geneva, Switzerland) has announced that it has signed up GlobalFoundries Inc. to be an additional source of devices made using 28-nm and 20-nm fully depleted silicon-on-insulator (FDSOI) technology. As part of the same deal ST is opening up the FDSOI process to let GlobalFoundries offer the process to other customers.
ST said that the "high-volume" availability of products in its proprietary FDSOI manufacturing process would help it produce higher performance, lower power mobile devices.
Grenoble research institute Leti, SOI wafer maker Soitec and IBM have been ST's partners in the development of the FDSOI process, and ST has increased FDSOI sourcing capacity by adding GlobalFoundries to its own pilot line capability at Crolles, France.
The 28-nm FDSOI is scheduled to be available for prototyping by July 2012 while 20-nm FDSOI is under development and is scheduled to be ready for prototyping by 3Q13.
The FDSOI manufacturing process technology has been selected by ST subsidiary ST-Ericsson for its NovaThor mobile phone platform.
In FDSOI transistors the electrical
conduction channel that forms between source and drain is confined to
the ultra-thin silicon layer under the gate oxide and above the SOI buried oxide. Source: ST-Ericsson.
"FD-SOI is ideally suited for wireless and tablet applications, where it provides fully-depleted transistor benefits using conventional planar technology, and this arrangement with GlobalFoundries ensures our customers will have a secure source of supply," said Joel Hartmann, STMicroelectronics corporate vice president responsible for digital manufacturing and process R&D at ST, in a statement.
"Porting libraries and physical IPs from 28-nm bulk CMOS to 28-nm FDSOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FDSOI is identical to bulk, due to the absence of MOS-history-effect," said Philippe Magarshack corporate vice president of design at ST, in the same statement.
Magarshack said that FDSOI can be used either for high performance or for low leakage current by biasing the substrate, and this can be done dynamically. In addition FDSOI can be taken down to low voltage to provide superior energy efficiency to bulk CMOS, he added.
Related links and articles:
ST, ST-Ericsson commit to SOI, says Soitec
FDSOI less 'risk' than FinFETs, says SOI body
IEDM: SuVolta transistor operates down to 0.4-V
Intel FinFETs vary, may need SOI for shrink, says GSS
Intel FinFETs are less fin and more triangle