SAN JOSE – Intel Corp.’s second run at the graphics market is catching some badly needed traction.
Supercomputer maker Cray announced today it will use in its high profile Cascades system Knights Corner, the first chip in Intel’s Many Integrated Core family. The chip, now branded Xeon Phi, will act as a co-processor, following a trend of supercomputers using x86 CPUs and graphics processors together to tackle highly parallel jobs at relatively low power consumption rates.
Separately, Intel said Knights Corner, its first Xeon Phi chip, is up and running and will be in production by the end of the year using its 22 nm tri-gate process. The chip will sport more than 50 x86-like cores and be offered as a PCI Express module with 8 Gbytes DRAM and GDDR memory.
Intel apparently has a supercomputer in its internal labs running the Xeon Phi chips that scored 119 teraflops on the Linpack benchmark and landed in 150th place on the latest version of the Top 500 list also released today. The system, called Discovery, uses 2.6 GHz Xeon E5-2670 processors along with Xeon Phi co-processors in an Infiniband cluster.
Intel measured a single Xeon Phi delivering a teraflops performance. Thanks to its x86 cores, it can run PC server applications as a standalone node, something graphics co-processors used in other supercomputers cannot do. Intel said it will more fully describe the Xeon Phi, its cores and programming model later in the year.
Supercomputers and technical workstations will be the first applications for Xeon Phi, however Intel has broader aims for the family. Currently 57 systems on the latest Top 500 list use graphics processors as accelerators, up from 39 six months ago. Nvidia supplied 53 of them, and IBM and AMD each supplied two.
The systems are typically clusters using thousands of processors. They target so-called high performance computing (HPC) apps, such as complex simulations. The Phi brand name reflects the largely scientific and technical nature of the apps.
Eventually, Xeon Phi could be used to run so-called big data and cloud computing apps at the high end of enterprise computing when such jobs require highly parallel chips. “All are possible targets for Xeon Phi,” said Raj Hazra, general manager of Intel’s high performance computing group.
“We see Xeon Phi as a viable candidate as we move to intensive big data apps such as with our Eureka products for analytics,” said Peter Ungaro, chief executive of Cray. “As we get much larger data sets in the world of big data, Xeon Phi will be an interesting candidate for those apps,” he said.
Peter Ungaro said Cray will announce its Cascades system in early 2013.
the Brookwood quote is disappointing, since he seems to have missed the point: it's not about x86 ISA, but rather the programming model we all know and love. anyone who has spent time rewriting code to suit the moving target of GPUs will appreciate a relatively normal memory model, threads, caches, shared memory and message passing. the Joules-per-flop argument is a good and interesting one, but it naively assumes that every workload is trivially malleable into the rather rigid model that GPUs provide.
the rash of large and relatively power-efficient Bluegene machines also questions the claim that efficient computation requires the GPU model...
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.