SAN FRANCISCO – A consortium touting fully depleted silicon-on-insulator (FDSOI) technology for mobile computing applications presented a united front this week in promoting the process technology as a viable alternative to Intel’s FinFET manufacturing approach.
ARM, IBM, Soitec and STMicroelectronics along with foundry partner Globalfoundries and R&D organizations like CEA-Leti made their case for the FDSOI approach at the Semicon West conference here. They also stressed the need for “collaborative innovation” as new mobile technologies grow in complexity and cost. “The need to collaborate has never been more important,” said Gary Patton, vice president of IBM’s Semiconductor R&D Center.
The chip makers make up the core of the SOI Industry Consortium, and its members essentially operate like a “virtual IDM,” or integrated device manufacturer, Patton added.
Every part of the semiconductor supply chain must do its part if the emerging chip technology is to succeed, added Subramani Kengeri, vice president of design solutions at Globalfoundries, which announced in June that it will work with ST on 28- and 20-nm devices based on FDSOI technology.
With growing pressure to boost the performance of mobile devices while at the same time reducing power consumption, “Partnering is the name of the game,” argued Phillippe Magarshack, vice president of ST’s Technology Research and Development Group. “Doing everything on your own [doesn’t] make sense.
ST’s mobile chip joint venture ST-Ericsson announced earlier this year that it will use planar FDSOI technology in its next-generation NovaThor mobile application processor.
Magarshack said ST will tape out the first 28-nm chips based on planar FDSOI technology next month, and it expects to begin sampling devices by the end of this year.
In FDSOI transistors, the electrical
conduction channel formed between source and drain is confined to
the ultrathin silicon layer under the gate oxide and above the SOI buried oxide. (Source: ST-Ericsson)
Proponents of the low-power approach maintain it will extend the battery life of smart phones and tablets by as much as 30 percent. CEA-Leti, the French chip R&D organization that holds key patents on FDSOI technology, claims it also can boost the speed of mobile devices by as much as 20 percent while providing, for example, an additional four hours of Web browsing on a mobile device.
It sound like a battle between planer FD SOI by new IBM alliances versus FD Trigate FinFETs by Intel has been declared. The key word here is FD (fully depleted) because both 22-nm transistor for IBM and Intel must be fully depleted to suppress the leakage current or short channel effects. Recently, Leti at the 2011 SOI conference has showed that ultra-thin/un-doped 6nm Si film is required for 22/20nm FDSOI to suppress the leakage current. For the 14nm FDSOI an extremely thin 4nm or less Si film may be required. However, Soitec can’t deliver such an ultrathin 6/4nm film in manufacturing. What Soitec can deliver is 12nm Si film and 25nm BOX for 22/20nm nodes. IBM and its alliance members also published FD SOI with 6.5/7 nm Si films at 2012 VLSI Symposium, but these are test chip data, not manufacture-able by Soitec.
Meanwhile, for FD finFETs the fin width (W) less than Lg (gate length) or W Lg is only required to suppress the leakage current. It means for 22nm node the fin W can have 21nm or less versus 6nm for FDSOI, and for 14nm node the fin W of 13nm or less versus 4nm for FDSOI. This is enormous advantage for manufacturability of 22/14nm FD finFETs compared with FD SOI. Furthermore, the trigate fins can be doped to adjust Vt, and manufacturability of the tri-gate fins dictates the device scaling. That is why Intel FD FinFETs is in high Volume manufacturing for several months, but FD SOI is not and will not be. The battle is over! S kim
@michigan. the Leti figure you're citing for FD-SOI Si thickness is *post-processing". The current and next-gen wafers from Soitec et al meet all the requirements. This was explained very clearly by Bruce Doris of IBM a couple years ago, who said (and it is still true), "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. " http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/ A lot has happened since you posted this comment -- I think you may find that the battle has just begun...
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