SAN JOSE – Engineers will get the first look inside new x86, Power and Sparc microprocessors at the Hot Chips conference next month. The event will cast a wide net that includes chips for cellular base stations and 3-D stacks.
Advanced Micro Devices will describe Jaguar, a low power x86 core. It is a follow on to Bobcat, a dual-issue core running on as little as 1W and initially implemented in 40nm technology when it was first describedin 2010.
Intel will push the x86 in the opposite direction in what is likely to be the first technical disclosure about Knights Corner, its multicore x86 chip for high-performance systems. In June, Intel said the chip, now branded Xeon Phi, will pack more than 50 x86 cores and 8 Gbytes memory in a module to ship before the end of the year.
For its part, IBM will describe two new microprocessors. The Power7+ is likely a process upgrade of the 45nm Power7, first detailed at Hot Chips in 2009. IBM has since launched several systems using the CPU, including a new line up earlier this year.
Big Blue also will try to break its own speed record with a new z-Series chip detailed at the event. The IBM z196 hit 5.2 GHz using 45nm technology and was described in a February 2011 paper.
For its part, Oracle will discuss its next-gen CPU, the Sparc T5 supporting eight-way multiprocessing. The 16-core chip is a 28nm upgrade to the eight-core T4 described at Hot Chips last year.
Separately, Applied Micro will provide some insights into its X-Gene design, a 64-bit ARM-based server system-on-chip. It was first shown in a simulation last year.
The conference will highlight trends in communications processors as well, including chips from Cavium and Qualcomm for the emerging sector of small cell base stations. Separately, Ethernet specialist Solarflare will present a paper on an ASIC that uses FPGA technology.
Hot Chips will also discuss 3-D chip stacks in a full-day tutorial. In addition, researchers from the University of Michigan will discuss their Centip3De design, a 64-core stack.
In a break with tradition, the August 27-29 event will be held at the Flint Center in Cupertino this year rather than at Stanford University.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.