LONDON – Processor IP licensor ARM Holding plc (Cambridge, England) and foundry chip maker Taiwan Semiconductor Manufacturing Co. Ltd. have signed a multi-year agreement to work together to optimize next-generation 64-bit ARM processor cores for FinFET process technology.
The agreement extends their collaboration beyond the 20-nm node, which TSMC (Hsinchu, Taiwan) is preparing to start manufacturing in 2013.
The collaboration is expected to show results in a 16-nm CMOS manufacturing process that will ramp in TSMC's wafer fabs in the second half of 2015. Rival foundry UMC has licensed a 20-nm FinFET manufacturing process from IBM.
The ARM-TSMC agreement specifically covers the delivery of ARM processor cores on a FinFET manufacturing process. It covers 64-bit ARM processors based on the ARMv8 architecture, Artisan physical IP and TSMC's FinFET process for use in mobile and enterprise markets.
The collaboration helps both parties as TSMC needs real-world designs to fine tune and prove its FinFET process and ARM gets early validation of its designs and a chance to optimize the designs for power, performance and area, thereby encouraging early adoption by licensees.
"By working closely with TSMC, we are able to leverage TSMC's ability to quickly ramp volume production of highly integrated SoCs in advanced silicon process technology," said Simon Segars, executive vice president and general manager of ARM's processor and physical IP divisions, in a statement.
"This collaboration brings two industry leaders together earlier than ever before to optimize our FinFET process with ARM’s 64-bit processors and physical IP," said Cliff Hou, vice president of TSMC R&D, in the same statement. "We can successfully achieve targets for high speed, low voltage and low leakage, thereby satisfying the requirements of our mutual customers and meeting their time-to-market goals."
Over the last few months TSMC has been unable to provide enough 28-nm wafers for some of its leading customers, although uncertainty remains about whether this is the result of lower than expected yields on certain designs or higher than expected demand.
thank you Peter, if that is the case then it is business is as usual and the announcement doesn't mean much...TSMC was always asking their leading customers what to build next, I remember that from 15 years back dealing with them, they would be silly not to do so (unless they would prescribe to Steve Jobs's approach of not listening to what the customer wants as the customer doesn't really know what it wants ;-)...Kris
I am not sure it is being optimized for one microprocessor architecture.
It is more like TSMC is using ARM to make sure the process works with real-world designs. They have to check it against something and ARM is prepared to make the IP available, put in the engineering hours and so.
The advantage to ARM is speed to market for its customers. But I am sure the process will run MIPS, for example, or could be tweaked for MIPS thereafter and relatively quickly.
It is very interesting to see that the silicon process at the foundry is now being optimized for a particular microprocessor architecture. However, it is not clear to me what that exactly entails. Will another processor vendor not being able to take advantage of the same process when fully developed? Kris
A business contact described tsmc technology roadmap as follows:
1. 28nm is the key advanced node for volume production (tsmc 28nm capacity ramp will be ~150,000 wafers/month by E2013. Might be expanded to 200K E2014)
2. 20nm will be smaller (20nm capacity in Tianan E2016 ~50K wafers/month). less interest do to cost of double patterning 64nm metal
3. 16nm is really Finfet with 20nm like design rules since EUV is not ready and triple patterning is too costly for 45nm metal. Since there is no die size reduction and wafer price is 20-30% higher...they don't see mobile market adopting and hence foundry will not really ramp 16nm until/if EUV or EB is ready?2018?
so after 20nm ... no cost reduction for several years and a slow down in moores law
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.