LONDON – Processor IP licensor ARM Holding plc (Cambridge, England) and foundry chip maker Taiwan Semiconductor Manufacturing Co. Ltd. have signed a multi-year agreement to work together to optimize next-generation 64-bit ARM processor cores for FinFET process technology.
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The agreement extends their collaboration beyond the 20-nm node, which TSMC (Hsinchu, Taiwan) is preparing to start manufacturing in 2013.
The collaboration is expected to show results in a 16-nm CMOS manufacturing process that will ramp in TSMC's wafer fabs in the second half of 2015. Rival foundry UMC has licensed a 20-nm FinFET manufacturing process from IBM.
The ARM-TSMC agreement specifically covers the delivery of ARM processor cores on a FinFET manufacturing process. It covers 64-bit ARM processors based on the ARMv8 architecture, Artisan physical IP and TSMC's FinFET process for use in mobile and enterprise markets.
The collaboration helps both parties as TSMC needs real-world designs to fine tune and prove its FinFET process and ARM gets early validation of its designs and a chance to optimize the designs for power, performance and area, thereby encouraging early adoption by licensees.
"By working closely with TSMC, we are able to leverage TSMC's ability to quickly ramp volume production of highly integrated SoCs in advanced silicon process technology," said Simon Segars, executive vice president and general manager of ARM's processor and physical IP divisions, in a statement.
"This collaboration brings two industry leaders together earlier than ever before to optimize our FinFET process with ARM’s 64-bit processors and physical IP," said Cliff Hou, vice president of TSMC R&D, in the same statement. "We can successfully achieve targets for high speed, low voltage and low leakage, thereby satisfying the requirements of our mutual customers and meeting their time-to-market goals."
Over the last few months TSMC has been unable to provide enough 28-nm wafers for some of its leading customers, although uncertainty remains about whether this is the result of lower than expected yields on certain designs or higher than expected demand.
Related links and articles:
ASML outlines a FinFET process 'two-step'
MEMC introduces SOI wafers for FinFET over oxide
Qualcomm signs UMC, Samsung for 28-nm chips, says report
UMC licenses IBM technology for 20-nm FinFETs