LONDON – ARM CEO Warren East is not concerned that Intel Corp. is developing a lead in process technology over the foundries that ARM licensees usually deal with. This is despite the fact that FinFET technology for ARM processors may not be in volume production until the second-half of 2015, according to foundry Taiwan Semiconductor Manufacturing Co. Ltd.
The use of FinFETs, where transistors stick up above the wafer surface, is considered to offer improved performance of transistors and to reduce leakage current in the off-state. Intel is already manufacturing in volume using in a 22-nm FinFET CMOS process while TSMC is attempting to ramp up planar 28-nm CMOS for is customers.
Nonetheless East told EE Times that ARM and TSMC together lead Intel in the system-on-chip (SoC) technologies where they compete with Intel. "We are concerned about integrated SoC. For SoC Intel is manufacturing using 32-nm high-k metal gate planar CMOS. TSMC is manufacturing using 28-nm high-k metal gate. That doesn't sound like a massive lead to me. If anything you could argue that TSMC is ahead."
East said that Intel's 22-nm FinFET is being used for high-volume PC chips but it would be no easy matter to make an SoC device with an extensive range of peripheral circuits in that process.
Intel has smartphone and tablet computer designs based on its Atom-based 32-nm Medfield processor. Intel is expected to manufacture its Atom low-power processor in the 22-nm FinFET CMOS process in 2013 in an architecture called Silvermont. Merrifield could be a 22-nm FinFET implementation for high-end smartphones.
With regard to the 16-nm FinFET process from TSMC and a 20-nm FinFET process from UMC East said: "It's hard to say exactly when it [FinFET for ARM] is going to arrive."
ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm.
I don't know exactly what Warren East meant but i took it to mean that a PC processor has a lot of CPU and not many other cores while an mobile device app processor has not much CPU and a lot of additional cores, with different digital and mixed-signal requirements.
All that IP, which Intel may have in 32-nm HKMG, has to be moved across to 22-nm FinFET.
Looks like your right.
Intel marketing is "good". They had us believing 10x lower leakage with trigate. Turns out 3x worse. So a factor of 30x marketing versus reality.
Let's see how they market the news when they switch to SOI.
I think you are mis-using the numbers here to get to 30x. It is always important to reference what is being compared against.
Intel 'tri-gate' FinFETs may well be superior to planar bulk CMOS, which is what most other companies are offering at present.
But Intel triangular FinFETs are a few percent inferior to rectangular FinFETs on bulk silicon
And rectangular FinFETs on bulk silicon are 2 to 3.5 times worse than FinFETs-on-SOI, according to GSS. As yet nobody is making FinFET-on-SOI although it may come.
So Intel FinFETs may be the best for leakage performance in the market at present but not quite as good as previously hoped because of triangular cross-section, which may have been adopted for manufacturing reasons.
Here is the data. Intel 22nm device specs were published at vlsi 2012. Leakage current is 1 to 100nA/um. Foundry for mobile 28nm SOC is 10pA/um to 10nA/um. Foundry mobile is 10X to 100X lower depending on device.
Intel will have a finfet soc in market in 2013. Since its not in market we don't know leakage. Intel will improve finfet and improve leakage but my guess it will match foundry leakage (not beat it)
Can you share your reference that intel is shipping lower leakage with finfet than Foundry and what leakage number you are using vs ( 1-100nA/um I ref.)
Intel does not have
Here is some more Intel leakage data. I understand there is confusion in media on this. Another data point on this is from Intel's 22nm product.
See Toms hardware comparing 3.5 Ghz parts idle power increase for 22nm
trigate compared to 32 planar : 71W vs 66W. Transistor leakage is a key component of idle power. see next quote in article as well. "Intel admits that it didn’t do much of anything to cut Ivy Bridge’s power consumption beyond its adoption of 22 nm lithography. It’s not surprising, then, that idle power use doesn’t really change compared to last generation."
So product shows ~ same leakage, ~same performance (3.5Ghz).
Explaining this unexpected result on leakage and performance could be
a great article.
SoCs have up to three different voltages with corresponding gate oxide thicknesses. I/O typically uses 0.18 um 3.3 V for example. The finfet cost and complexity has to be included with non-finfet portion for overall SoC process cost-effectiveness consideration.
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