LONDON – Intel Corp. (Santa Clara, Calif.) has announced the integration of a 3G HSPA radio frequency transceiver with power amplifiers on a single 65-nm die.
The chip is designed in a standard 65-nm foundry process as offered by GlobalFoundries, Taiwan Semiconductor Manufacturing Co. Ltd. and United Microelectronics Corp., said Stefan Wolff, vice president of the Intel Architecture Group, in email correspondence with EE Times.
The Smarti brand is used for all Intel mobile communications cellular RF transceiver products and was established more than 10 years ago by Infineon Technologies AG. The brand was acquired by Intel with the Infineon wireless business unit.
The SMARTi UE2p integrates power management and sensors and allows direct connection to the battery. The chip supports multiple 3G dual-band configurations for use with Intel's HSPA modem chips.
"This will allow our customers to introduce lower-cost 3G handsets and support the transition of the machine-to-machine market segment toward 3G-based connected devices to help enable the Internet of things," said Wolff.
The Smarti UE2 is proven product that has shipped in various high end smartphones, UE2 stands for UMTS/EDGE 2nd generation. The p has been added for the integrated 3G power amplifiers.
A specification is available but only under a non-disclosure agreement and for selected customers, Wolff told EE Times. The specification is not intended to be published.
Intel said the Smarti UE2p chip would be available as samples in the fourth quarter of 2012.
This article is a data point for Arm CEO article.
Intel does have leadership for CPU but process lead means for mobile SOC is more than Moore law. Process lead in mobile is about SOC integration.
PA are one of the hardest RF components to integrate in CMOS so Intel's announcement is significant. So when intel sets out to introduce this new chip it uses a foundry 65nm technology. Mr .East point was Mobile chips require higher levels of integration ( RF and power transistor being just two examples) which are not even supported today in intels 22nm finfet).
This article is a bit curious. Integration of a 3G 65nm CMOS PA onto the transceiver is a major advance in RF functional integration. Yet the article talks more about integration of power management and sensor integration than about PAs- about which it says nothing more than mentioning the PA. Then it talks about lower cost handsets and M2M applications. Are we talking about a PA capable of full handset transmit power, or are we talking about a dialed-down output power PA? Is it possible the term "power amplifier" mistakenly got interchanged with "power management"?
I can only tell you what Intel tells me and they are often skimpy on engineering information. As it says above: there is no datasheet and information is only available to special customers under NDA.
But Intel definitely says it integrates power amplifiers (that is what the p stands for) and Intel says the 65-nm device is good for 3G handsets and for M2M applications.
Intel executive Stefan Wolff told me the design will be manufactured by a foundry and then mentioned all of GlobalFoundries, TSMC and UMC.
He has seen the story as it appeared and is happy that it says power amplifiers.
I guess they could be dialed-down PAs but then there would be no logistical benefit for full handset operation, which Intel says this device brings.
INVENTORS - DO NOT TRUST INTEL!!!
I invented a CPU cooler - 3 times better than best - better than water. Intel have major CPU cooling problems - "Intel's microprocessors were generating so much heat that they were melting" (iht.com) - try to talk to them - they send my communications to my competitor & will not talk to me.
Winners of major 'Corporate Social Responsibility' awardS!!!
Huh!!!! When did RICO get repealed?"
INVENTORS - DO NOT TRUST INTEL!!!
BTW, I have the evidence - my competitor gave it to me.
BBTW, I am prepared to apologise to Intel if;
• They can show that the actions were those of a single individual in the company, acting outside corporate policy, and:
• They gain redress on my behalf.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.