LONDON – Fabless networking chip firm Cavium Inc. (San Jose, Calif.) has announced that it is planning to deliver a family of multicore system-chips based on full custom cores designed to implement the 64-bit ARMv8 instruction set architecture from ARM Holdings plc (Cambridge, England), The chips will be aimed at "cloud" and data center opportunities, the company said.
The so-called Project Thunder processors will be offered alongside Octeon and Nitrox processor families. Octeon processors are based on core licenses from MIPS Technologies Inc. (Sunnyvale, Calif.). Cavium said it has chosen to use MIPS or ARM architectures based upon the target end market, industry trends, installed software base, ecosystem and customer demand.
Project Thunder will provide a scalable family of 64-bit ARMv8 processors incorporated into an SoC architecture that includes workload accelerators and industry standard I/O ports. The company did not indicate how many cores it is expects family members to include or how soon they would be available in the market. Cavium did say it would announce details at a later date.
Cavium is aiming to provide a 10 times improvement in the price, performance and power over rivals' alternatives for the target applications.
The ARMv8 architecture from processor IP licensor ARM is the first to include 64-bit execution.
ARM has tipped two ARMv8 cores that are being designed for implementation in 20-nm silicon and expected to come to market in 2014. These are codenamed Atlas and Apollo (see ARM tips gods and heroes roadmap).
"Cavium is a leading multicore processor vendor and has delivered highly differentiated SoCs including a range of ARM processor-based products for many years," said Warren East, CEO of ARM, in a statement.
In the same statement Syed Ali, CEO of Cavium, said: "The adoption of the ARMv8 architecture combined with ARM's extensive software ecosystem will enable us to extend the reach of our innovative, high performance multicore SoCs to new customers and applications."
Pretty good move on ARM's behalf. After 4 years of touting their Quadcore-A9 they realized that it simply does not cut it for Server Applications. A9 will always be memory limited since it is a 32-bit CPU.
The question remains: Did they really miss the boat of 64-bit since the train has left the station!!
So much for MIPS! What is curious is that Cavium decided to license the architecture and implement its own cores - similar to AppliedMicro's X-Gene, although APM has a few years head start on them. This can only be good for the ARM camp with another david arming itself against the Intel goliath.
I wonder if cavium is going to stick to its tried and tested sea of wimpy cores like the octeon or will they try to target higher performance.
Earlier this year, LSI announced it was licensing ARM for next-generation base station SoCs. It uses PowerPC today.
IMHO, We are clearly seeing a consolidation around ARM (low power) and Intel (high performance) in embedded, just as we are in mobile computing.
MIPS and PowerPC will come under pressure to maintain vibrant ecosystems in the long term.
Certainly seems that way. Freescale has also announced ARM processors. The last stand-out will be Broadcom which is still heavily invested in MIPS. I wonder if they are regretting the $4B they spent on Netlogic to get its MIPs design.
Am I missing something? Where are the mainstream ARM licensees? Aren't they as interested in ARMv8?
It seems odd that a PowerPC vendor and a MIPS vendor neither with any ARM experience are the chosen vehicles for ARM 64-bit. Certainly Freescale and Marvell have a strong portfolio of the kinds of functionality you surround the core with in the server world.
@Peter, how can Cavium provide 10 times improvement in performance and power simultaneously ? If I am not wrong they are mutually exclusive right i.e if its power efficient performance will degrade and vice-versa.
this sort of ARM-ism seems to be quite the fad - playing, I suppose, on the clear low-power nature of the ARM in everyone's phone. but in purely engineering terms, what is it about ARM that makes it inherently more power efficient? sure, x86 has a baroque instruction encoding, but is that really where the power savings are? ARM is slightly funky itself (funkiness is mostly proportional to age...) - but MIPS is relatively clean, and it isn't making the same "inherently more efficient than x86" waves.
in other words, what would happen if you put ARM into the x86 context: socketed CPU driving a 2x 64b ddr3/1600 memory interface. would there still be some sort of power savings (also assuming the same process technology)?
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