SAN JOSE – The Hybrid Memory Cube Consortium released to its members an initial draft of interface specifications for its 3-D DRAM memory stack. The group is now in final review of the specs with plans to release them publicly near the end of the year.
The group has so far defined two specifications—an interface protocol and a short-reach physical layer channel. The PHY is optimized for use connecting a memory cube and chips sitting multiple inches of printed circuit board traces away in a networking system.
The group will also define an ultra short reach PHY. It aims to extend less than three inches and is optimized to connect the cube with die, probably on a single multi-chip module.
Only members can get access to the initial drafts and provide input on them until the review process is complete and the specs are made public at the end of the year. The group is still open to accepting new members.
The group is led by Micron and Samsung. Other members include Altera, ARM, Hewlett-Packard, IBM, Microsoft, Open-Silicon, SK Hynix and Xilinx.
The spec is primarily targeted at high-performance networking, industrial, and test and measurement applications. IBM has also suggested it will use the cubes for high-end servers. The cubes contain both DRAM memory chips and a memory controller.
Previously, Micron said it will deliver 2 and 4 Gbyte versions of the cubes in early 2013, providing aggregate bi-directional bandwidth of up to 160 Gbytes/second.
Separately, the Jedec standards group is working on a follow on to the 12.8 Gbit/second Wide I/O interface that targets mobile applications processors. The so-called HB-DRAM or HBM effort is said to target a 120-128 Gbyte/second interface and is led by the Jedec JC-42 committee including representatives from Hynix and other companies.