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Memory-cube group issues initial draft specs

8/14/2012 12:00 PM EDT
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resistion
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re: Memory-cube group issues initial draft specs
resistion   8/14/2012 12:34:37 PM
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Seems the TSV bandwidth is wasted on flash.

zanfar
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re: Memory-cube group issues initial draft specs
zanfar   8/14/2012 3:20:11 PM
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It was my understanding that the HMC consortium was primarily concerned with DRAM memory--not Flash. http://www.hybridmemorycube.org/technology.html

rick merritt
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re: Memory-cube group issues initial draft specs
rick merritt   8/14/2012 6:29:00 PM
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Yes the Memory Cube is for DRAM not flash. My mistake. The story above has been corrected.

Rchandta1
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re: Memory-cube group issues initial draft specs
Rchandta1   8/14/2012 9:23:45 PM
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Agreed stacking DRAMs has advantage. But I can't understand the rest. It is tightly coupled with the memory controller, so there is power and latency benefits. But it seems to force the processor away from the memory controller. Many processors have integrated DRAM controllers; so the stacking scheme seems to negate their advantage.

resistion
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re: Memory-cube group issues initial draft specs
resistion   8/14/2012 11:47:31 PM
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Agreed, so Intel not participating is important to wonder about.

rick merritt
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re: Memory-cube group issues initial draft specs
rick merritt   8/15/2012 4:15:47 AM
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Yes, Intel, AMD, HP and Oracle--basically the computer industry outside IBM--has been silent so far on its 3-D memory strategy. Presumably they are headed down the Jedec route.

David Brown
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re: Memory-cube group issues initial draft specs
David Brown   8/16/2012 8:41:57 AM
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Why would you want a DRAM controller in a processor? The DRAM controller handles things like timings for the different row selects, bank access, refresh, etc. You want these as close to the DRAM chip as possible. The reason memory controllers became integrated into processors is not because that's the best place for them - it was to avoid the extra chip, buses and latency caused by having the controller on a separate device between the processor and the memory (and sharing bus bandwidth with PCI and other buses). The reason the controller is not in the DRAM chips today is because the chip process needed for controller logic is very different from that needed for the DRAM cells, so it would be hugely expensive to put them on the same die. If you put the memory controller inside the DRAM cube, then the bus between the processor and the memory can be simpler and faster, and the memory controller can be more optimal for the dram banks it is controlling (including wider bus access and local cache inside the cube). The potential here is not just to increase bandwidth, but also to lower latency - especially in servers with large memories and ECC.

Wayman
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re: Memory-cube group issues initial draft specs
Wayman   8/16/2012 6:36:23 AM
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For Wide I/O, I suppose the target should be 12.8GBytes/s which is proposed by Intel.

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