LONDON – In a return to the 20th century days of electromechanical computation IBM and STMicroelectronics are working on a project to enable a low-power processor made from nanometer-scale mechanical relays.
The European Commission likes the idea and has put IBM Research Zurich in charge of a European research project that aims to produce a logic process that is based on nanometer-scale relays that remain compatible with conventional CMOS transistor logic. The advantage of such a system would be much lower off-state power consumption as leakage current would be considerably reduced.
Alongside IBM and STMicroelectronics NV (Geneva, Switzerland) are academic researchers from the Ecole Polytechnique Federale de Lausanne, Kungliga Tekniska Hoegskolan (KTH), and the universities of Bristol and Lancaster.
The three-year collaborative research project has a budget of 3.96 million euro (about $5.0 million) of which the European Commission is providing 2.44 million euro (about $3.1 million).
The motivation for the research is that as transistors have been miniaturized leakage power consumption is becoming as large as active power consumption and this is a particular issue for emerging applications such as autonomous sensors nodes, wireless communications and mobile computing.
The NEMIAC (Nano-Electro-Mechanical Integration And Computation) project aims to develop a process based on what it calls nano-electromechanical (NEMS) switches suitable for embedded systems and offering 3-D integration with CMOS. The researchers are being asked to show a magnitude improvement in energy efficiency with no performance penalty compared with solid-state. The process is also expected to have higher radiation resistance and higher temperature operation than CMOS.
Mechanical relay as replacement for transistor. Source: NEMIAC
The relays are expected to have a footprint of less than 3-micron by 3-micron and demonstrate a switching time of the order of 10 nanoseconds. Prooving the reliability under billions of switching operations will be an important task prior to commercial deployment. The term "bug" is said to have been introduced into the computing industry because of the propensity for
The project is expected to produce a number of digital logic designs as proof of the process and innovative circuit architectures for low-power applications. In parallel design and simulation methodologies are going to be developed to aid exploration of the design-space and demonstrate the feasibility of a small microprocessor.
One possible advantage would be that this takes us back to the polarity insensitive and bidirictional current flow inherent in a relay. Back when logic was routinely made from relays, those attributes were routinely taken advantage of to create systems that weren't strictly boolean in nature. The result was fewer relays (and lower power consumption).
You must be joking... THIS is where we're headed? Somehow, I doubt that Intel and others are too worried about the potential competition. Still, it does cause one pause, and in thinking about it, I can see all sorts of low-end applications that beg for as close to zero power if were possible to achieve. This may help.
No matter how small you make a mems switch, the switching speed is still in kHz or at best barely reaching MHz. Although it is small, there is still inertia associated with the metal that is being moved. For those applications that are okay with kHz clock rates but almost no power consumption and extraordinarily radiation hard, this could be what you are waiting for.
This is actually not true; the UC Berkeley group has already demonstrated ns response times and sub-micron features. The technology promises to scale well. The issues are really system-level: device advantages often get lost when the constraints of an entire system are considered.
Okay... indeed, they have demonstrated 10ns switching in 90nm technology. I went back to a Berkeley MEMS paper presented at ISSCC 2010 titled "Prospects for MEM Logic Switch Technology" by Tsu-Jae King Liu, et. al. A very interesting and well written paper. Please contemplate the implications of the following statement pulled from the cited paper. "Ideally, relay endurance should exceed ~3×10^14 cycles, e.g. so that a relay- based microcontroller for embedded sensor applications
could operate reliably for 10 years at 100 MHz clock frequency and 0.01 average transition probability." The clock restrictions implied in that statement are significant. Since this is an emerging technology, perhaps they will find a chemistry that enables higher reliability, which translates into greater reliability and longer life or significantly higher transition probability. Higher clock rate... perhaps.
I have built MEMS switches for RF applications and I don't want to rain on anyone's parade, but it also makes me well aware of fundamental physics. i hope they prove me wrong and will gladly drink to their success.
Interesting discussion, we had very interesting talks on this topic at emerging technologies symposiums (www.cmoset.com)...mechanical devices look slow but at nanoscale they can be actually pretty fast, ns or so...they also look large but again at nanosacel they can be quite small so you can put fair amount of them on IC...having said that there is no way they can replace MOSFETs, they can only add value by providing extra functionality like lower leakage switches...Kris
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