SAN FRANCISCO—EDA and IP vendor Cadence Design Systems Inc. said Tuesday (Sept. 4) that the first products in its DDR4 SDRAM PHY and memory controller IP family have been proven in silicon on TSMC's 28-nm high-performance for mobile applications process and its 28-nm high-performance process.
Cadence (San Jose, Calif.) said it has received and characterized multiple versions of its DDR PHY and controller IP in 28-nm silicon based on advanced drafts of the DDR4 standard.
The proposed DDR4 standard, anticipated to be released by Jedec later this year, is expected to offer users performance benefits over DDR3, Cadence said. DRAM devices adopting the DDR4 standard are expected to have 50 percent higher operational frequency and double the memory capacity of DDR3 devices while reducing the power consumed in the DRAM by as much as 40 percent per bit transferred, according to Cadence.
"DDR4 is going to be the next big thing in DRAMs, but its signaling is challenging to handle," said Jim Handy, an analyst at Objective Analysis, in a statement released by Cadence. "As PCs migrate to DDR4 DRAMs, this standard will become the volume leader, giving it a price advantage that will be impossible to ignore. ASIC designers who want to take advantage of that pricing are likely to need a lot of help putting a reliable interface on their products."
Cadence said its PHY family includes a high-speed implementation of the DDR4 PHY that exceeds the data rates specified in the DDR-2400 draft, meeting the requirements of next-generation computing, networking, cloud infrastructure, and home entertainment devices, while offering interoperability with current DDR3 and DDR3L standards. Related stories:
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