SAN JOSE, Calif. – Intel Corp. is not providing details, but it has disclosed plans that confirm industry speculation of recent weeks: The x86 giant is developing a next-generation interconnect it will integrate in future Xeon and Atom server processors addressing a range of uses from supercomputers to microservers.
The news is timed to compete with an announcement later on Monday (Sept. 10) from Advanced Micro Devices about the Freedom Fabric it acquired with startup SeaMicro. AMD is expected to try to make that interconnect an industry standard for its server CPUs, and probably those of emerging ARM-based server SoCs.
Interconnects--sometimes called fabrics--are key to linking tens to hundreds of thousands of processors in a broad range of servers. They are used in everything from the world’s most powerful supercomputers to large cloud computing data centers and microservers, dense chassis packed with processors generally used as Web servers.
The industry has been anticipating an Intel move into interconbnects after three recent acquisitions. In April, Intel bought an interconnect group from Cray for $140 million. In January, it acquired the Infiniband chip business of QLogic for $125 million, and in July 2011 it bought Fulcrum for an undisclosed sum.
“We are putting a salable fabric into the processor using the assets we have with our recent acquisitions,” said Raj Hazra, general manager of Intel’s technical computing group. “We think this integration happens much sooner than end of decade as some people have suggested, tying it to exascale supercomputers,” he said.
The new Intel interconnect aims to cover the waterfront in applications. At the low end, it could be used in microservers to link a hundred or more processors at tens of GBytes/second with latencies of less than 1,000 nanoseconds. At the high end, it ultimately will scale up to linking hundreds of thousands of processors at hundreds of GBytes/second at latencies measured in tens of nanoseconds.
The interconnect will appear in Xeon, Xeon Phi and Atom processors geared for such servers. It’s not clear when Intel will relesase details of the new interconnect and CPUs using it, although some details may emerge from this week’s Intel Developer Forum.
“We haven’t finished the road map planning,” said Hazra.
Most of the work defining the interconnect appears to be going on inside Intel with the help of a few software companies and systems integrators. “We have strong software ecosystem,” he said.
The technology likely will emerge as a set of new capabilities layered on to the exsiting Quick Path Interconnect Intel uses as its proprietary processor bus. The technology may use elements of existing Ethernet, Infiniband and proprietary interconnects inclouding RapidIO, now being proposed as a competing standard for ARM server SoCs.
“We’ve looked at all the potential solutions and their pros and cons,” Hazra said.
Intel collaborated with SeaMicro on the startup's Atom- and Xeon-based server designs until AMD bought the startup earlier this year. “We know what their fabric was and it was interesting for a microserver class products line, but I have no idea where it has evolved,” he said.
Other than stating that Intel is doing something that can scale from interconnecting micro-servers to exascale and that it will appear before the end of the decade, this does not have any details.
Intel being intentionally vague or is this just vapour-ware?
Intel is pre-announcing its plans in hopes of distracting people from having any interest in AMD's Freedom Fabric or whatever other alternatives the ARM server SOC folks such as Calxeda are developing.
Unfortunately, this is another area where different companies will promote different solutions instead of coming together to develop a consistent standard, which common in the server world.
While Intel’s announcement may not fool people (as you put it), if companies have to make a choice, they are much more likely to choose the one touted by the industry leader, even if it does not represent an industry standard. Others will just sit on the sidelines until an industry standard is developed.
rick & jim, whole im late finding this news, i thought it would be clear to you both this is just a half assed response thats not even a "Cache Coherent Network" to ARM's existing initial 1 Terabit/s rated Cache Coherent Network Interconnect
"CoreLink CCN-504 is the first in a family of products. It enables a fully-coherent, high-performance many-core solution that supports up to 16 cores on the same silicon die. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems"
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.