SAN FRANCISCO Ė Longer battery life and better graphics lead a laundry list of improvements in Intelís next-generation CPU, Haswell. Intel described its first new architecture for its 22-nm tri-gate transistor process at its annual developer forum here.
Two- and four-core client versions of Haswell will ship in PCs by April, said Dadi Perlmutter, general manager of the Intel Architecture Group, in a keynote address here. He showed early versions of the chip running in prototype systems at less than 8W on jobs that drew more than 17W on Intelís existing Sandy Bridge CPUs.
"A lot of the consumer impact will be in significantly longer battery life and better graphics performance," said Kevin Krewell, senior analyst with The Linley Group (Mountain View, Calif.) and editor of Microprocessor Report. "But a lot of the real benefits in the CPU won't come until you optimize and compile for the chipís enhanced AVX2 code," he said.
The architecture will serve a broader range of systems than any previous Intel CPU, extending from fanless tablets to high-end servers. A new ultra-low active power state called S0ix leads a handful of power management advances in Haswell, enabling a 20-fold reduction in idle power
"When a Haswell platform is doing little work, it is almost always in this new state," said Per Hammarlund, an Intel Fellow.
Haswell also transitions between high and low power states faster than existing x86 chips. In addition, it uses new low power modes for interfaces such as Serial ATA, PCI Express and USB.
Haswell runs at less than 8W on jobs that require more than 17W on Intel's current CPUs.
In graphics, Haswell offers a new GT3 version that replicates the key blocks in the existing Ivy Bridge graphics die. That results in about twice as much graphics umph as current Intel CPUs.
The new AVX2 instructions include a fused multiple-add that the chip can execute twice per cycle, doubling floating point performance of the Sandy Bridge architecture. Other new instructions help cryptography jobs or ease the work of making use of parallel tasks.
For example, the chip supports two forms of transactional memory for automating ways large databases can be updated. The capability will be particularly useful for server versions of Haswell, which may be more than a year away.
Haswell sports the same types and sizes of caches as previous chips. However, Intel has doubled the bandwidth of its L1 and L2 caches to boost performance.
Krewell estimates existing software will see about a 10 percent gain in CPU performance. But much higher gains are possible for code that uses the new instructions, he said.
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