SAN FRANCISCO – Intel Corp. has found a way to create a 10-nm process technology using immersion lithography. In addition, the processor giant is on track to start making chips in a 14-nm process technology before the end of next year, an Intel fellow said in a talk here.
The 10-nm process would debut in 2015 or later. It would require quadruple patterning for some mask layers but “it’s still economical,” said Mark Bohr, director of Intel’s technology and manufacturing group, speaking to EE Times after a talk at the Intel Developer Forum here.
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Bohr did not reveal details of either Intel’s 14- or 10-nm process plans. His comments focused only on technical feasibility.
The company has long worked to develop extreme ultraviolet (EUV) lithography and recently agreed to invest $4.1 billion in tool maker ASML to drive it forward. “EUV is very important to us, and that’s why we invested in ASML, but we have multiple paths that we pursue such as immersion with multiple patterning,” Bohr said.
Intel expects to use at least double patterning in some layers of some chips at 14 nm. If immersion is used at 10 nm, more layers will require double patterning, and some will even require quadruple patterning, he said.
At 14 nm, Bohr said, "the increased wafer costs [associated with double patterning] is still being offset by improved density, so our cost per transistor continues to go down with each generation on a very steady trend."
That trend would continue, he suggested, even if immersion is used at 10 nm. As of today, “EUV is later than I would like, and I can’t count on it for sure,” he said.
“We are probably the last company continuing to stay on a pace of having a new process technology every two years or so,” Bohr said in his talk.
In theory Intel’s Trigate FinFETs can extend to 10nm beyond as long as lithography can permit because for FinFETs to be fully depleted to suppress the leakage current or short channel effects the fin width (W) less than gate length (Lg) is only required. For 10nm node and below, however, new physical phenomena not seen in wide fin W will occur. The fin W at bottom of the fin for 10nm node and below may approach 6nm or less and 5nm at top of the fin. However, for the fin W with such an extremely thin 6nm may hit the CMOS scaling wall or the end of the Moore’s Law because of the quantum mechanical effects imposed by the structural quantum confinement. It means in simple terms that the electrons within such extremely thin 6nm fin W do not behave like classical particles any more, but instead act as waves. As a result, drift and diffusion based classical semiconductor physics is no longer applicable. Instead, the electron behavior is now described by the quantum mechanical physics based Schrodinger’s wave equations and is subjected to Heisenberg’s uncertainty principle.
The impact of such quantum confinement on the electrical characteristics is a significant increase in threshold voltage Vt due to the mobility degradation caused by decrease in the inversion layer thickness. The Vt increase depends on how thin the fin W is. But this adds to the variation in Vt due to the short channel effect with varying Lg. The other more critical effect is very large variations or uncertainties in transistor transfer characteristics such as Vt, Id/Vg, ID/Vd, DIBL, SS (sub-threshold slop), and SRAM noise. These are physical limits derived from quantum mechanical effects, limiting to the channel length to 10nm node with fin W of 6nm. Process variations not considered here could further adversely impact the variability of finFETs electrical characteristics. Therefore, in my opinion the 10 nm node with fin W 6nm or less will not be manufacturable or the end of CMOS scaling. S Kim
For the cost-effective part to make sense, we need the half-pitch or the distance between metal wires to shrink, to enable more transistor connections per unit area. If this distance does not shrink, but only a particular feature shrinks, it could actually add process complexity and some cost.
I believe that this is a fairly standard tactic. The process node only identifies the smallest feature that can be reliably resolved and patterned. There shouldn't be any roadblock to making a 90nm sized transistor in 20nm but I'm not a chip designer. Anyone out there that can comment?
Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.
Around 10 nm, you cannot merely have a radically new technology come in for one area but a whole package of technologies needed for devices, interconnect, etc. Plus we are now at the scale of electron mean free paths.
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