SAN FRANCISCO – Intel Corp. has found a way to create a 10-nm process technology using immersion lithography. In addition, the processor giant is on track to start making chips in a 14-nm process technology before the end of next year, an Intel fellow said in a talk here.
The 10-nm process would debut in 2015 or later. It would require quadruple patterning for some mask layers but “it’s still economical,” said Mark Bohr, director of Intel’s technology and manufacturing group, speaking to EE Times after a talk at the Intel Developer Forum here.
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Bohr did not reveal details of either Intel’s 14- or 10-nm process plans. His comments focused only on technical feasibility.
The company has long worked to develop extreme ultraviolet (EUV) lithography and recently agreed to invest $4.1 billion in tool maker ASML to drive it forward. “EUV is very important to us, and that’s why we invested in ASML, but we have multiple paths that we pursue such as immersion with multiple patterning,” Bohr said.
Intel expects to use at least double patterning in some layers of some chips at 14 nm. If immersion is used at 10 nm, more layers will require double patterning, and some will even require quadruple patterning, he said.
At 14 nm, Bohr said, "the increased wafer costs [associated with double patterning] is still being offset by improved density, so our cost per transistor continues to go down with each generation on a very steady trend."
That trend would continue, he suggested, even if immersion is used at 10 nm. As of today, “EUV is later than I would like, and I can’t count on it for sure,” he said.
“We are probably the last company continuing to stay on a pace of having a new process technology every two years or so,” Bohr said in his talk.
In his talk, Bohr said many features in the 22nm process use 80 pitch features, a size chose for this generation because they can be single patterned.
He did not say anything about double patterning at 22nm or quintuple patterning on any process.
I have no doubt that Intel can get to 10 nm with quadruple patterning, but will they be able to suppport a reasonable business model once they get there? And what happens after 10 nm? Is that the end of scaling unless and until EUV litho kicks in at reasonable cost?
Yes, question is not if 10nm can be done but what economic advantage does it bring after spending Billions and Billions of $. With 80nm pitch used for 22nm that would mean ~40nm metal pitch for 10nm. There is no cost effective way to print. Plus even if lithography breakthrough, parasitic capacitance and line resistance are going to be so large chips will be slower and higher power.
Around 10 nm, you cannot merely have a radically new technology come in for one area but a whole package of technologies needed for devices, interconnect, etc. Plus we are now at the scale of electron mean free paths.
Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.