SAN FRANCISCO -- PCI Express, the I/O backbone of PCs and servers, is getting a low-power extension that will take it into Ultrabooks, tablets and smartphones starting next year. The enhanced interconnect will draw two to four times less power while helping mobile devices link to high-performance peripherals such as 60-GHz wireless networking controllers and solid-state drives.
The PCI Special Interest Group expects to approve by the end of the year a new version of its low level software for PCIe 3.0. The code will run on the M-PHY physical layer chips defined by the MIPI Alliancethat creates handset interfaces.
The two groups signed a deal Monday (Sept. 10), cementing their collaboration. The PCI SIG will also create a version of its next-generation PCIe 4.0 software for M-PHY.
“We’ve been chasing for months the Holy Grail of getting to a lower power version of PCI Express because we know that’s where the volume is and where the users are,” said Al Yanes, chairman of the PCI SIG.
Specifically, the PCI SIG will define a new variant of its physical link layer software to run the M-PHY. The code will enable multiple asymmetrical lanes, dynamic bandwidth negotiation and lower electromagnetic interference.
“We are making PCI Express mobile friendly,” said Brian Carlson, vice chairman of the MIPI Alliance.
Last year, a senior Marvell engineering manager called for a mobile interconnect to link his applications processor to an external 802.11ac controller. The link needs to deliver 1.1Gbits/s while consuming less than 38 milliwatts on a 1.8-volt supply, he said.
The new M-PHY combined with PCI Express addresses that need, said Carlson. M-PHY was first defined in April 2011 at 1.25 Gbits/s, an update released in June 2012 runs at 2.9 Gbits/s and a third generation coming next year will hit up to 5.8 Gbits/s.
The link is defined over copper traces at up to 30 cm and over optical lengths up to five meters. For its part, PCIe 3.0 supports up to 8 GTranfers/second.
As many as three billion devices using MIPI interfaces could ship in 2012, said Carlson. Many of them use an older D-PHY link, running at about 500 Mbits/s, geared for mobile displays and cameras.
The new variant of PCIe over M-PHY addresses active power, the biggest consumer of energy. The PCI SIG released in June an addition to its PCIe 3.0 spec addressing idle power, a technology Intel incorporated into the design of its next-generation processor, Haswell.
"The new M-PHY combined with PCI Express addresses that need, said Carlson. M-PHY was first defined in April 2011 at 1.25 Gbits/s, an update released in June 2012 runs at 2.9 Gbits/s and a third generation coming next year will hit up to 5.8 Gbits/s."
-- any information on what the associated power numbers are for these solutions? Would also be interesting to know what processing node this is happening on.
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