LONDON – A tutorial presentation at the upcoming ARM TechCon exhibition and conference, taking place October 30 to November 1 in Santa Clara, will discuss the mix of challenge and opportunity represented by the 14-nm manufacturing node which lies two or three years away from mass production, if the lithography fates allow.
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Lars Liebman, a distinguished engineer at IBM, and Greg Yeric, a senior R&D engineer with ARM, are both set to speak in a 50-minute presentation scheduled for 11:30am on Tuesday October 30.
The speakers are expected to address how difficult patterning for IC definition is likely to interact with non-planar structures – the fin-shaped FinFETs that rise above the silicon surface and that expected to be in use at that node.
The tutorial is set to review the status of extreme ultraviolet (EUV) lithography and explain how double-patterning using optical lithography can bridge gap until EUV becomes available. Information on how to ease the complexity for multipatterning will be disclosed. The tutorial is also set to review fundamental principles of the FinFET, explore the FinFETs impact on both physical IP and at a higher level processor IP. In other words what the implications of the FinFET are for forthcoming ARM processor cores and designs fashioned around them.
The presentation is set conclude by exploring expectations for power, performance, area and cost of ICs at the 14-nm node.
Liebman's technical focus in IBM's semiconductor R&D center has been on lithography-friendly design and is currently on design-technology co-optimization for sub-resolution patterning of leading-edge technology nodes. ARM's Yeric focuses on design-technology co-optimization, technology prediction and IP R&D.
Tuesday is also set to conclude at 5.00pm with a panel session that will discuss FinFETs but with particular regard to how the introduction of such transistors will revolutionize mobile electronics. The panel is entitled The era of extreme mobility; the finflection point.
But for those who wish to understand if FinFETs in bulk silicon are more trouble than they are worth, Horacio Mendez, executive chairman of the SOI Industry Consortium is set to discuss the use of fully depleted silicon-on-insulator (FDSOI) manufactuing process technology at the 20-nm node. Mendez' presentation is set for 2:10pm on Tuesday (Oct. 30).
The paper is set to describe oxide-isolated FinFETs and planar transistors and argue that they have advantages over their bulk counterparts. It is set to include device- and circuit-level data that benchmarks the power and frequency performance. The presentation will also address IP portability, which is important for design migration.
ARM TechCon, due to take place October 30 to November 1 at the Santa Clara Convention Center, is organized by UBM Electronics, the publisher of EE Times.
I think 20 nm won't be popular for a while. It is also quite possible some will go direct from 28 nm to 14 nm, after a few years. If the patterning technology is quite expensive, you'd need to make up with higher density sooner.
Ah but if we prevented development of 16-nm/14-nm and 10-nm nodes until all the 28-nm to 20-nm transition problems were solved, the industry would be severely delayed in ever getting to 16/14-nm.
Working on multiple challenges and production nodes has been with us for a long time and one of the ways in which Moore's predictive law has been fulfilled....to date.
"FinFETs in bulk silicon are more trouble than they are worth", Horacio Mendez,
...that does look to be the case for the "16nm node" which is "20nm design rule finfet on bulk silicon".
I can't see doing a SOC in FinFET unless a planar device is also offered for all my analog/mixed signal circuits and low leakage always on circuits.
How about we not talk as an industry about 10nm or 14nm until we admit at even today at 20nm will still don't have a viable 20nm strategy. Today's 20nm due to the double patterning just does not offer much if any improvement over 28nm.
Even over the next 5 years it does not appear cost per transistor will be lower in 20nm vs 28nm.
I do hear foundry has found many issues with Intel's 22nm bulk Fin design point for SOCs. Top issues is supporting range of threshold voltages required for SOCs. Intel's approach which dopes the fins causes too much leakage variation and matching issues for circuit operation less than 0.9-1V supply voltage.
This is all consistent with Intel's own 22nm SOC now delayed until end of 2013. Rumor is Intel might be going to SOI for 22nm SOC technology version to fix this issue. Would allow intel to implement a real undoped body FinFET.
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