BOSTON – Microcontroller makers and software developers welcomed Intel to the embedded software party following the PC giant’s announcement of a framework for embedded middleware. They agreed with Intel’s motives, expressing a mix of hope that the new effort could add value and doubt it could cover the diverse waterfront.
Intel announced last week its Intelligent Systems Framework to secure, manage and aid connectivity for embedded systems. It uses a combination of code from its McAfee and Wind River divisions along with Intel’s VPro management software for PCs.
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The framework intends to smooth a path for a growing class of sensors that gather and communicate data as part of an Internet of Things. Because it is tied to use on x86 processors, it is likely to see most widespread use on gateways and hubs, becoming a de facto standard that end nodes based on microcontrollers will need to support.
Vendors at Design EAST said they already support multiple standards and approaches to embedded security, management and connectivity. They weren’t aware of Intel’s initiative and expressed concerns it might not fit the memory budgets of typical microcontrollers.
“I’m happy to see another effort at setting standards, but it’s no panacea because no one solution will fit all the requirements of embedded systems—the area is too diverse,” said Robert Van Andel, president of Allegro Software Development Corp. (Boxborough, Mass.)
Allegro got its start 17 years ago with the development of an embedded Web server that fit into as little as 10 Kbytes of memory. It helped pioneer embedded versions of Secure Sockets Layer and Transport Layer Security as well as secure Web clients. It supports management and connectivity standards defined by the IETF, UPnP and DLNA.
“In security, the problem is not the lack of standards so much as getting people to use the ones we have,” said Van Andel.
Representatives from Microchip, STMicroelectronics and other microcontroller makers expressed concerns that the Intel software may be too big for the memory footprint of their chips. For example ST’s 32-bit MCUs support from 8 Kbytes flash and 16 Kbytes SRAM to a Mbyte flash and 192 Kbytes SRAM with a sweet spot at about 128 Kbytes flash and 48 Mbytes SRAM.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.