SAN JOSE, Calif. – The Jedec standards group posted the specification for Synchronous DDR4, the next generation for mainstream DRAMs used in everything from laptops to servers. The spec defines an interface delivering up to 3.2 GigaTransfers/second and is Jedec’s first to include features supporting 3-D stacking.
“It is likely that higher performance speed grades will be added in a future DDR4 update,” Jedec said in a press statement. The DDR4 interface covers signaling at rates that start 1.6 GT/s, a rate already being exceeded by some DDR3 parts.
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The DDR4 interface supports stacks of up to eight memory devices presenting only a single signal load. To enhance efficiency and bandwidth, DDR4 chips support two or four selectable bank groups, allowing simultaneous activation, read, write or refresh operations in each bank group. DDR4 speeds require AC timing parameters to be defined and measured in a new way.
“The new standard will enable next-generation systems to achieve greater performance, significantly increased packaging density and improved reliability with lower power consumption,” said Joe Macri, an AMD executive who chairs Jedec’s JC-42.3 group on DRAMs, in a statement.
“Improvements in performance and power consumption make DDR4 an attractive memory solution for the next generation of enterprise and consumer products, and we look forward to driving this technology into the marketplace,” said Robert Feurle, vice president for DRAM marketing at Micron.
Samsung and others also expressed support for the standard which DRAM makers have been implementing in modules for some time. Jedec will host a two-day workshop on the new spec in Santa Clara, Calif., on Oct. 30 and 31.