ARM earlier this year announced its new ARM Cortex™-M0+ processor. In this article, we will introduce the new processor and explain how it can bring additional advantages to your embedded products.
The Cortex-M0+ processor builds on the successful Cortex-M0 processor released in 2009. The Cortex-M0 processor provides excellent code density and best in class energy efficiency in about the same silicon area as 8-bit and 16-bit processors.
[Designing with ARM? Get a 10% discount on ARM TechCon 2012, Oct. 30 - Nov. 1 in Santa Clara. Click here to register for the year's biggest and best live event for the ARM community. ]
Since its release, the Cortex-M0 processor is the fastest ever licensed ARM processor core, with more than 50 licensees by the end of 2011. Additionally, ARM design teams have continued to work closely with its partners on possible improvements. That work formed the concept of the Cortex-M0+ processor.
ARM partners highlighted several criteria in demanding applications that could not be addressed by the existing processor solutions. One of the top requirements was to achieve even lower power and much greater energy efficiency. In order to satisfy these requirements, the Cortex-M0+ processor was completely redesigned from the ground up while keeping complete instruction set and debug compatibility. For the first time, ARM has produced a processor design with a two-stage pipeline, and used the opportunity to improve the performance while maintaining a very similar maximum frequency. The overall result is very encouraging. When compared to the existing Cortex-M0 processor, the Cortex-M0+ processor consumes only two thirds of the dynamic power in our power analysis test, when running Dhrystone loops.
The lower power consumption of the processor is certainly important, but how about system level power consumption? By moving to a two-stage pipeline design, the branch shadow of the processor is reduced. As a result, the number of accesses to flash memory is cut. Flash memory power often contributes the majority of the power consumed in a microcontroller so any reduction in Flash accesses has then a very direct effect on the overall power.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.