LONDON – STMicroelectronics has selected Samsung's foundry business unit for the production of ICs using a 32/28-nm high-K metal gate manufacturing process.
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The deal provides ST with alternative supply of 28-nm silicon. In the past ST has worked with Taiwan Semiconductor Manufacturing Co. Ltd. in the past as a supplier of leading-edge chips but during 2012 the Taiwanese foundry has been unable to meet the demand for 28-nm CMOS from its customers leading a number of them to announce plans to find other sources of silicon.
ST is also a manufacturer of leading-edge chips itself. ST has opted to manufacture circuits using a fully-depleted silicon-on-insulator (FDSOI) process for leading-edge chips it makes at 28- and going on to 20-nm. It remains unclear is whether the deal with Samsung has any implications about ST's commitment to the FDSOI process it has chosen to pioneer itself.
ST has been working with Samsung's foundry for some time and the relationship has already produced tape-outs of a dozen system-on-chip devices for mobile, consumer and networking applications. Tape-out represents the completion of the design phase although it can take several months for a chip to pass through manufacturing and be approved for sale.
"We have successfully started production of STMicroelectronics' new-generation 32/28nm SoC products," said Kwang-Hyun Kim, executive vice president with Samsung's foundry business unit, in a statement. "A foundry relationship with ST demonstrates our commitment to advanced process technology and our 32/28nm HKMG process-technology leadership. We have aggressively ramped 32/28nm capacity and will continue to deliver the most advanced process solutions to our customers."
"In addition to delivering waves of innovative new products, another key to ST's success in each of our target markets is working with industry leaders," said Jean-Marc Chery, chief-technology officer for STMicroelectronics, in the same statement. He added that ST and Samsung had worked together on process development in a body called the International Semiconductor Development Alliance.
I believe there are two challenges to be faced: a. Effective and efficient FDSOI wafer supply. 160K/month would be not enough in production phase.
b.$500 per wafer is too expensive to be adopted. For production, $250-300 would be affordable target.
Article mentions "... already produced tape-outs of a dozen system-on-chip devices for mobile, ..."
any idea which mobile SoC is referred to here? Is it same NovaThor SoC?
FDSOI helps in multiple power saving techniques like dynamic body biasing, on chip regulator, sub-clock power gating etc., how these feature compares to HKMG process technology?
thank you Adele for a clear and comprehensive explanation...BTW, would you have any interested in editing a small book on SOI? (I have been recently approached by one of the publishers I work with)...Kris
Hi Kris -- yes, it's been a confusing issue for everyone! Basically the wafer mfgs quote top Si thickness of the wafers they ship, while the chipmakers quote the Si thickness once they're done processing the device -- which is always less.
Bruce Doris of IBM explained it nicely in an ASN article from 2010 http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/: "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. To reach full industrialization, we need a high-volume supply of wafers with thickness variation of less than +/-0.5nm with corresponding wafer-to-wafer uniformity." So now Soitec's shipping wafers for FD-SOI with Angstrom-level uniformity, meeting all the requirements. SEH (the world's biggest wafer mfg), recently told SemiMD that they are, too (http://semimd.com/blog/tag/seh/ )
BTW, back in 2010, IBM was getting post-processed Si thickness of 3.5nm, which could meet the requirements of the 11nm node, so you can imagine they've made all kinds of progress since then!
And as Soitec's pointed out on their website: "Uniformity of the top silicon layer of Soitec FD-2D wafers [[their wafers for FD-SOI]] is guaranteed to within +/-5Ĺ at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. For planar fully depleted SOI (FDSOI) CMOS technology, uniform thickness is crucial to controlling transistor Vt variations." Their current product spec sheet http://www.soitec.com/pdf/Soitec-FD-2D-product_brief.pdf indicates top Si of the FD-SOI wafer (this is pre-processed, as indicated above) down to 10nm.
Hope that helps!
ST is doing FD-SOI -- make no mistake about it -- it's a game changer. See today's interview with ST's JM Chery http://www.advancedsubstratenews.com/2012/10/exclusive-asn-interview-sts-jean-marc-chery-on-fd-soi-manufacturing/ He said: " ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other. Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013."
Interestingly, he also says they're moving right to 14nm with it.
@Michigan -- Soitec has no trouble with the wafers. SEH is also a supplier. Don't confuse the starting thickness with the finished thickness. Starting wafers have slightly higher top Si thicknesses, and some is etched away during manufacturing, hence what looks like a discrepancy is not.
Also, re: Samsung, Chery recently told David Manners that " And we can use Samsung for SOI if we need to". (see http://www.electronicsweekly.com/Articles/04/09/2012/54458/st-a-competitive-follower-in-process.htm)
I think ST will remain committed to analog, mixed-siganl and MEMS manufacturing. But it could be about to announce the withdrawal from digital IC production?
As you point out ST has spoken of several dropped days of production at Crolles and Catania in Q4.
And then disclosed that an updated strategic plan for the company is due to be presented in December.
It will be interesting to see what that contains.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.