Breaking News
News & Analysis

Samsung, ST sign foundry deal

9/28/2012 08:50 AM EDT
22 comments
NO RATINGS
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 3   >   >>
Kresearch
User Rank
Rookie
re: Samsung, ST sign foundry deal
Kresearch   10/5/2012 9:36:34 PM
NO RATINGS
I believe there are two challenges to be faced: a. Effective and efficient FDSOI wafer supply. 160K/month would be not enough in production phase. b.$500 per wafer is too expensive to be adopted. For production, $250-300 would be affordable target.

Adele.Hars
User Rank
Rookie
re: Samsung, ST sign foundry deal
Adele.Hars   10/5/2012 2:29:34 PM
NO RATINGS
Sure! Let's talk.

xx19xx
User Rank
Rookie
re: Samsung, ST sign foundry deal
xx19xx   10/5/2012 2:01:37 PM
NO RATINGS
Article mentions "... already produced tape-outs of a dozen system-on-chip devices for mobile, ..." any idea which mobile SoC is referred to here? Is it same NovaThor SoC? FDSOI helps in multiple power saving techniques like dynamic body biasing, on chip regulator, sub-clock power gating etc., how these feature compares to HKMG process technology?

Kresearch
User Rank
Rookie
re: Samsung, ST sign foundry deal
Kresearch   10/2/2012 8:11:58 AM
NO RATINGS
Wow: 5A corresponding to ~2 Si atomic layers. To control Si thickness range less than 5A on SOI within whole 300mm wafer is amazing.

krisi
User Rank
CEO
re: Samsung, ST sign foundry deal
krisi   10/1/2012 9:21:17 PM
NO RATINGS
thank you Adele for a clear and comprehensive explanation...BTW, would you have any interested in editing a small book on SOI? (I have been recently approached by one of the publishers I work with)...Kris

Adele.Hars
User Rank
Rookie
re: Samsung, ST sign foundry deal
Adele.Hars   10/1/2012 9:11:12 PM
NO RATINGS
Hi Kris -- yes, it's been a confusing issue for everyone! Basically the wafer mfgs quote top Si thickness of the wafers they ship, while the chipmakers quote the Si thickness once they're done processing the device -- which is always less. Bruce Doris of IBM explained it nicely in an ASN article from 2010 http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/: "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. To reach full industrialization, we need a high-volume supply of wafers with thickness variation of less than +/-0.5nm with corresponding wafer-to-wafer uniformity." So now Soitec's shipping wafers for FD-SOI with Angstrom-level uniformity, meeting all the requirements. SEH (the world's biggest wafer mfg), recently told SemiMD that they are, too (http://semimd.com/blog/tag/seh/ ) BTW, back in 2010, IBM was getting post-processed Si thickness of 3.5nm, which could meet the requirements of the 11nm node, so you can imagine they've made all kinds of progress since then! And as Soitec's pointed out on their website: "Uniformity of the top silicon layer of Soitec FD-2D wafers [[their wafers for FD-SOI]] is guaranteed to within +/-5Ĺ at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. For planar fully depleted SOI (FDSOI) CMOS technology, uniform thickness is crucial to controlling transistor Vt variations." Their current product spec sheet http://www.soitec.com/pdf/Soitec-FD-2D-product_brief.pdf indicates top Si of the FD-SOI wafer (this is pre-processed, as indicated above) down to 10nm. Hope that helps!

krisi
User Rank
CEO
re: Samsung, ST sign foundry deal
krisi   10/1/2012 4:59:22 PM
NO RATINGS
thank you Adele, could you clarify the SOI wafer thickness issue pls? why would anyone quote the starting thickness if the final thickness is all that matters? Kris

Adele.Hars
User Rank
Rookie
re: Samsung, ST sign foundry deal
Adele.Hars   10/1/2012 4:07:32 PM
NO RATINGS
ST is doing FD-SOI -- make no mistake about it -- it's a game changer. See today's interview with ST's JM Chery http://www.advancedsubstratenews.com/2012/10/exclusive-asn-interview-sts-jean-marc-chery-on-fd-soi-manufacturing/ He said: " ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other. Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013." Interestingly, he also says they're moving right to 14nm with it. @Michigan -- Soitec has no trouble with the wafers. SEH is also a supplier. Don't confuse the starting thickness with the finished thickness. Starting wafers have slightly higher top Si thicknesses, and some is etched away during manufacturing, hence what looks like a discrepancy is not. Also, re: Samsung, Chery recently told David Manners that " And we can use Samsung for SOI if we need to". (see http://www.electronicsweekly.com/Articles/04/09/2012/54458/st-a-competitive-follower-in-process.htm)

resistion
User Rank
CEO
re: Samsung, ST sign foundry deal
resistion   10/1/2012 9:20:45 AM
NO RATINGS
In 2009 ST went to GlobalFoundries for 40 nm because TSMC was having troubles then. It looks like history repeating similarly again.

Peter Clarke
User Rank
Blogger
re: Samsung, ST sign foundry deal
Peter Clarke   10/1/2012 8:57:29 AM
NO RATINGS
@FraAmelia I think ST will remain committed to analog, mixed-siganl and MEMS manufacturing. But it could be about to announce the withdrawal from digital IC production? As you point out ST has spoken of several dropped days of production at Crolles and Catania in Q4. And then disclosed that an updated strategic plan for the company is due to be presented in December. It will be interesting to see what that contains.

Page 1 / 3   >   >>
Top Comments of the Week
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.
Flash Poll