SAN JOSE, Calif. – Broadcom’s newly acquired NetLogic group is sampling an integrated 28-nm network processor, claiming it has a leap over competitors Cavium, Freescale and LSI. The XLP 200 family is the group’s first to target control as well as data plane jobs and the first to use a new accelerator block for handling some security features.
The chip comes in versions including one or two custom out-of-order MIPS cores that support four threads each at up to 2 GHz. They also build in a grammar processing engine that links incoming packets to the appropriate malware database for security searches, a function previously handled in software on general purpose cores.
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The chips also include hardware accelerators for deep packet inspection and regular expression computations. The accelerators act independently, requiring no help from the chip’s general-purpose MIPS cores.
Although the chips are sampling now, they won’t be in full volume production until the second half of 2013. The high-end systems such chips go into have design cycles for components of 6-18 months at companies such as Cisco and Hauwei, said Kelvin Khoo, a senior director of business development at Broadcom.
The former NetLogic group has a family of higher-end 40nm chips using more MIPS cores, targeted primarily at data plane processing. “We didn’t have a single- or dual-core product, so this rounds out our product line,” said Khoo.
Cavium, Freescale and LSI have all announced plans to support ARM cores in future chips for access networking systems at the entry level and midrange of their product lines where performance per Watt is a key issue. To date, Broadcom supports only MIPS cores.
MIPS cores meet both the performance and the performance per Watt needs of the mid- and high-end comms systems Broadcom targets, said Khoo. “In today’s comms market, you need the highest performance possible and MIPS is a unique architecture to get to performance per Watt,” he said.
One wonders where the breakpoint is between using general purpose processors vs packet processors, given Intel's talk about handling 40 Gbps at IDF last month. Its certainly a lot less investment to stick a pair of 40 Gbps NICs into a off-the-shelf machine than to design a network processor into a custom package. The network processor will be more energy efficient, and likely cheaper with volume, but at what volume? With network processors, one is forced to keep moving from vendor to vendor as either old solutions are discontinued or not updated.
I had a product based on the Motorola/Freescale C5, there were lots of plans for a successor, but the C5 didn't sell well, and after the Freescale spinoff, the successor was killed. Even if the successor hadn't been killed, we weren't seeing enough volume to afford to design a new board and migrate. I have another more recent design based on Cavium, but again, the volume isn't high enough to justify migrating to newer technology. General purpose processors look better and better, as lots of people make them, with design cycles more closely matching new device availability.
The line between "general purpose" processors and "embedded" processors is bluring. CPUs inside these new embedded processors are fairly high performance (at least in netlogics case - the cavium cpus have generally been lower performance but more in number). The embedded folks have more offloads and accelerators built in for specific applications which does result in improvement in performance. But this usually comes with some cost in customizing code and this then becomes sticky (great for the embedded guys).
As designs move from one ISA to another, the embedded customers may start demanding higher performance CPUs and not get tied into a specific accelerator (onloading vs. offloading). It is much easier to recompile code from MIPS to ARM e.g than having to port your security driver from one custom MIPS implementation to another.
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