For example, SRAM cells won’t get a full 50 percent shrink at 14 nm
without EUV, Ronse said. That’s because multiple patterning has some
limits in how closely it can place features.
“They can only catch
up if EUV becomes available,” Ronse said. “There [are] lot[s] of resources
going into development of light sources, so there is definitely a way to
get there, but it’s hard to estimate if it will be in two years,” he
Intel and TSMC recently committed billions of dollars to ASML (Eindhoven, Netherlands) which is developing the EUV systems.
also recently said it expects to make 14-nm chips next year and could
make 10-nm processors in 2015 using existing immersion lithography.
Without EUV, Intel believes it will have to write as many as five
immersion patterns on a chip which will take more time and money but is
IMEC now gets more than 60 percent of
production time with its ASML NXE 3100 EUV system installed here. “We
had quite some bumpy behavior in the first six months with average up
time declining from 50 to 10 percent,” due to problems with an older
light source, he said.
In its trials, IMEC has achieved device
resolution down to 16-nm half pitch with EUV. “EUV is most likely not
going to be used for all layers [in a chip], but for some critical
layers and will have to be aligned well for immersion,” said Ronse.
is also a problem. To date, IMEC has achieved alignment within 6 nm of
EUV and immersion layers on a chip. It needs to get down to alignment
within 2 to 3 nm, he said.
Intel's Bohr sees path to 10-nm chips
ASML won't get fooled again