LEUVEN, Belgium – Moore's Law, the engine of semiconductor innovation for decades, is losing steam due to delayed introduction of next-generation extreme ultraviolet lithography. That was the verdict of experts at the 2012 International Symposium on Extreme Ultraviolet Lithography.
EUV systems need light sources that are nearly 20 times more powerful than the ones used today to lay down patterns on next-generation chips that target sizes as small as 14 nm, Following a global symposium on the topic here, a group of lithography experts said that they hope to have the 200W EUV light sources by 2014—but it may take more time.
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Using less powerful light sources, researchers at the Interuniversity Microelectronics Centre (IMEC) here have created about 3,000 wafers using EUV in the past year. But the throughput of the multimillion dollar systems are still 15-30 times too slow for commercial chip makers such as Intel, Samsung and Taiwan Semiconductor Manufacturing Co.
Researchers have improved the power of light sources 20-fold over the past three years. But they must make similar heroic improvements in the next two years before EUV is ready for production, said Kurt Ronse, IMEC's director advanced lithography program, reporting on the conclusions of an EUV symposium in Brussels. The group also called for development of 500-1,000W EUV light sources by 2016.
As a result of the EUV delays “the [semiconductor] industry is no longer taking full steps, but implementing half nodes,” Ronse said. “They still call it 14 nm but it’s probably more like 16 or 17 nm,” he said.
Something they should have known. So much more energy absorbed from a shorter wavelength photon into a smaller space, obviously higher energy density needs to be dissipated into a larger volume to avoid unwanted material changes.
In one form or another, multiple patterning becomes necessary.
This has been known for years @resistion...I attended IEDM conference 20 years ago where this issue was discussed ;-)...talks about slowing of the Murphy's law started shortly after "the law" was established...I remember limits at 1 micron level considered insurmountable ;-)...but it might be true this time around...litho is clearly a huge challenge...but not the only one...Kris
Wow, that's quite a while back, if I read those papers, maybe I would have reconsidered joining this field, who knows ;-)
I guess saying scaling won't happen would be much riskier than saying a particular way of scaling won't happen.
"Without EUV, Intel believes it will have to write as many as five immersion patterns on a chip which will take more time and money but is still economical." Hope it is true. But when litho rework rate boomed with strigent process requirements in triple and above patterning, process window and yield are impaced severely. It will be hard to see economic advantages in dimension shrinking. It is happening in current 22/20nm processes(double pattern) and getting worse for 14nm and beyond. That is the reason why Intel/Samsung/TSMC(even nVidia) are urging 450mm progress in parallel to lower down process cost. Tons of hurdles ahead, Go engineers.
The EDA enablement of multi-patterning provides a path to maintain a path along Moore's law. The only hesitation has been cost. But what most people are ignoring is the fact that by the time they get an EUV system capable of the numbers they need it will probably cost more than multi-patterning with traditional steppers, and it may even need multi-patterning itself.
would it not be better to make a larger step and go to directed self-assembly (DSA)? multi-patterning feels very incremental with some gains due to smaller feature size and some losses due to lower throughput
The dimensional scaling is clearly reaching demising return and escalating challenges. The NV NAND vendor have recognized it and are shifting to monolithic 3D (see Blog piece by Israel Beinglass http://www.monolithic3d.com/2/post/2012/10/3d-nand-opens-the-door-for-monolithic-3d.html)
The logic vendor would sooner or later recognize it too (especially as the would need to carry the burden all by themselves)- the future of scaling is up - monolithic 3D
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