LEUVEN, Belgium – Moore's Law, the engine of semiconductor innovation for decades, is losing steam due to delayed introduction of next-generation extreme ultraviolet lithography. That was the verdict of experts at the 2012 International Symposium on Extreme Ultraviolet Lithography.
EUV systems need light sources that are nearly 20 times more powerful than the ones used today to lay down patterns on next-generation chips that target sizes as small as 14 nm, Following a global symposium on the topic here, a group of lithography experts said that they hope to have the 200W EUV light sources by 2014—but it may take more time.
[Get a 10% discount on ARM TechCon 2012 conference passes by using promo code EDIT. Click here to learn about the show and register.]
Using less powerful light sources, researchers at the Interuniversity Microelectronics Centre (IMEC) here have created about 3,000 wafers using EUV in the past year. But the throughput of the multimillion dollar systems are still 15-30 times too slow for commercial chip makers such as Intel, Samsung and Taiwan Semiconductor Manufacturing Co.
Researchers have improved the power of light sources 20-fold over the past three years. But they must make similar heroic improvements in the next two years before EUV is ready for production, said Kurt Ronse, IMEC's director advanced lithography program, reporting on the conclusions of an EUV symposium in Brussels. The group also called for development of 500-1,000W EUV light sources by 2016.
As a result of the EUV delays “the [semiconductor] industry is no longer taking full steps, but implementing half nodes,” Ronse said. “They still call it 14 nm but it’s probably more like 16 or 17 nm,” he said.
DSA is promising but a long road to become production worthy. It becomes more sensitive in Photoresist thickness, temperature and chemical variations. It usually is treated as alternative if EUV or multi patterning fails to meet market requirements.
Monolithic 3D is by far the best way to keep on integration while not increasing the overall power consumption. As for heat removal/thermal consideration, it is not much different than dimensional scaling as the monolithic scaling utilize very thin layers. In fact a detail paper on this issue resulted of a joint work with research group at Stanford university will be presented in the coming IEDM 2012
The advantage of monolithic 3D scaling that we could apply it to an older process yet achieve better benefits than the next node of dimensional scaling. I would expect that the 28nm or 20nm would be a good node to apply monolithic 3D as an alternative to 14nm or 10nm
Lithography is clearly a challenge (and not the only one)and at least it seems that it will need more time.Monolithic 3D with thin layers is an excellent path to continue Moore's Law. There are area that would need engineering such as heat removal and crosstalk but there are no "Red Brick Wall". And as the NAND vendors already adapting monolithic 3D for future scaling, there will be less vendors to support the escalating costs of dimensional scaling for lithography, transistors development etc.
Isn't monolithic 3D really just an area bump, with some plusses and some minuses? You could in principle also just make chips physically larger in 2-D. A 3-D chip with 2 physical layers is not easier to make than double patterning 1 physical layers, is it? Seems quite similar to a multichip module. My impression is most applications are after higher nodes not because they desperately need more than 10 billion transistors, but that they need better device parameters or cost per transistor.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.