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Moore's Law threatened by lithography woes

10/5/2012 01:26 PM EDT
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resistion
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re: Moore's Law threatened by lithography woes
resistion   10/6/2012 12:42:51 AM
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Basically, vertical scaling after horizontal scaling has stopped. But sequential patterning throughput, electrical and thermal considerations still limit vertical scaling.

Kresearch
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re: Moore's Law threatened by lithography woes
Kresearch   10/6/2012 1:45:09 AM
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DSA is promising but a long road to become production worthy. It becomes more sensitive in Photoresist thickness, temperature and chemical variations. It usually is treated as alternative if EUV or multi patterning fails to meet market requirements.

Or_Bach
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re: Moore's Law threatened by lithography woes
Or_Bach   10/6/2012 2:57:31 AM
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Monolithic 3D is by far the best way to keep on integration while not increasing the overall power consumption. As for heat removal/thermal consideration, it is not much different than dimensional scaling as the monolithic scaling utilize very thin layers. In fact a detail paper on this issue resulted of a joint work with research group at Stanford university will be presented in the coming IEDM 2012

resistion
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re: Moore's Law threatened by lithography woes
resistion   10/6/2012 4:32:35 PM
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Well it looks like even 11 nm by currently demonstrated EUV or DSA would require double patterning support. So what design rule to base the 3d on?

Or_Bach
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re: Moore's Law threatened by lithography woes
Or_Bach   10/6/2012 5:56:13 PM
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The advantage of monolithic 3D scaling that we could apply it to an older process yet achieve better benefits than the next node of dimensional scaling. I would expect that the 28nm or 20nm would be a good node to apply monolithic 3D as an alternative to 14nm or 10nm

resistion
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re: Moore's Law threatened by lithography woes
resistion   10/7/2012 3:44:17 AM
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With either litho or 3D pushing for thinner layers, the increasing dissipation of resistance and risk of crosstalk should be pushing back.

swu3
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re: Moore's Law threatened by lithography woes
swu3   10/7/2012 5:55:18 PM
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Lithography will be a fundamental limiter for all companies. It will many it hard for any single company to have even a 1 generation technology lead.

Or_Bach
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re: Moore's Law threatened by lithography woes
Or_Bach   10/8/2012 4:21:58 AM
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Lithography is clearly a challenge (and not the only one)and at least it seems that it will need more time.Monolithic 3D with thin layers is an excellent path to continue Moore's Law. There are area that would need engineering such as heat removal and crosstalk but there are no "Red Brick Wall". And as the NAND vendors already adapting monolithic 3D for future scaling, there will be less vendors to support the escalating costs of dimensional scaling for lithography, transistors development etc.

jeffreyrdiamond
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re: Moore's Law threatened by lithography woes
jeffreyrdiamond   10/8/2012 4:23:57 PM
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Isn't monolithic 3D really just an area bump, with some plusses and some minuses? You could in principle also just make chips physically larger in 2-D. A 3-D chip with 2 physical layers is not easier to make than double patterning 1 physical layers, is it? Seems quite similar to a multichip module. My impression is most applications are after higher nodes not because they desperately need more than 10 billion transistors, but that they need better device parameters or cost per transistor.

Youself
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re: Moore's Law threatened by lithography woes
Youself   10/8/2012 5:02:25 PM
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May be so, but I've been hearing about the demise of Moore's Law for literally decades now. And in a few months we'll hear how the industry managed to get past the current hurdles. Repeat, rinse.

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