LEUVEN, Belgium – Moore's Law, the engine of semiconductor innovation for decades, is losing steam due to delayed introduction of next-generation extreme ultraviolet lithography. That was the verdict of experts at the 2012 International Symposium on Extreme Ultraviolet Lithography.
EUV systems need light sources that are nearly 20 times more powerful than the ones used today to lay down patterns on next-generation chips that target sizes as small as 14 nm, Following a global symposium on the topic here, a group of lithography experts said that they hope to have the 200W EUV light sources by 2014—but it may take more time.
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Using less powerful light sources, researchers at the Interuniversity Microelectronics Centre (IMEC) here have created about 3,000 wafers using EUV in the past year. But the throughput of the multimillion dollar systems are still 15-30 times too slow for commercial chip makers such as Intel, Samsung and Taiwan Semiconductor Manufacturing Co.
Researchers have improved the power of light sources 20-fold over the past three years. But they must make similar heroic improvements in the next two years before EUV is ready for production, said Kurt Ronse, IMEC's director advanced lithography program, reporting on the conclusions of an EUV symposium in Brussels. The group also called for development of 500-1,000W EUV light sources by 2016.
As a result of the EUV delays “the [semiconductor] industry is no longer taking full steps, but implementing half nodes,” Ronse said. “They still call it 14 nm but it’s probably more like 16 or 17 nm,” he said.
I strongly agree with your last statement and in fact the strongest value of integrated circuit is being integrated. Integrated function in one device instead of connecting many devices over PC board represent about an order of magnitude improvement in power performance and cost. An important differentiation to be made is between 3D IC using TSV vs. monolithic 3D. While the cost of devices using TSV is not lower but in fact higher the monolithic 3D IC provide cost reduction as we detailed in our Blog (http://www.monolithic3d.com/2/post/2012/06/is-the-cost-reduction-associated-with-scaling-over.html)
Just to clarify, Moore's Law was originally:
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase."
Stacking die can increase the number of components, but without any significant cost savings I'm aware of. That's not what Moore meant.
Moore's Law has been breaking down now for a decade, in that people like you and me, and practically every other engineer out there, no longer have any meaningful chance of developing a new state of the art chip in the latest process. Only a few remaining giant corporations can afford it, and they apply their fab technology to fewer and fewer high volume chips. The innovation that made Silicon Valley great is no longer being applied to the latest and greatest silicon. In 1988, I laughed at the 1.5 micron three-metal NMOS process used at HP, because everyone was on 1 micron CMOS by then. Anyone even one process node behind was literally a joke. Now days, there are many times more .35 micron tape outs than 28nm. I'm sorry, but Moore's Law is a corpse that is just still twitching...
EUV, unless some fundamental breakthroughs magically appear, will not save Moore's Law.
That said, 3D stacking is cool, and I hope it works out as you envision. There is enormous value in being smaller, if not cheaper.
Yes, I agree. Moore's Law is on going and if you look to the original Moore forecast (1965) it is about: " the number of transistors on integrated circuits doubles approximately every two years". Moore attribute it to three trends: Decrease dimension, larger die and improving the architecture. Monolithic 3D is part of the last two. We wrote more about in in our Blog (http://www.monolithic3d.com/2/post/2011/03/guest-contribution-entanglement-squared-by-zvi-or-bach.html)
Isn't monolithic 3D really just an area bump, with some plusses and some minuses? You could in principle also just make chips physically larger in 2-D. A 3-D chip with 2 physical layers is not easier to make than double patterning 1 physical layers, is it? Seems quite similar to a multichip module. My impression is most applications are after higher nodes not because they desperately need more than 10 billion transistors, but that they need better device parameters or cost per transistor.
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