SAN JOSE, Calif. – LSI Corp. and Calxeda Inc. are the first chip companies to license from ARM Holding plc a new on-chip interconnect developed for linking up to 32 cores on a die. ARM's CoreLink CCN-504, delivering throughput in the range of a terabit/second, will debut in LSI’s first ARM-based devices to be announced in February.
The initial version of the CoreLink interconnect will handle up to 16 cores, with plans to extend it in the future to support 32. LSI will use the interconnect on its next-generation Axxia communications processor to link a range of ARM cores—probably using the Cortex A15—as well as DSPs and accelerator blocks. LSI says it helped write code for the interconnect.
Calxeda, a developer of ARM-based processors and software for low-power servers, says it is already building its next
generation chips for datacenter servers using CoreLink technology.
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LSI likely will use the interconnect--known internally as "Dickens"—in a ring topology, but can also be configured as a mesh or crossbar. It scales beyond existing ARM Amba buses currently limited to linking eight cores.
The coherent link supports quality of service to the cores as well as to on-chip level 3 cache and DDR memory. Ultimately, other chip makers and OEMs will also be able to use the interconnect. LSI will employ it for both standard products and as part of its ASIC service.
“This is a game changer for industry and LSI,” claimed Tareq Bustami, director of LSI’s wireless networking business. “OEMs want to mix and match ASICs, standard solutions and combinations of the two,” said Bustami. “To do that effectively we need an interconnect anyone can use,” he said of the news announced at the Linley Tech Processor Forum here.
LSI and archrivals Applied Micro, Freescale and Cavium, who have previously supported only Power or MIPS cores, are now rolling out new lines based on ARM. They share a desire to leverage ARM’s broad ecosystem and its relatively high performance-per-Watt capabilities at a time when several 64-bit ARM cores are in the works.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.