SAN JOSE, Calif. -- Imagination Technologies is integrating details of process technologies at 28 nm and beyond into the designs of its graphics cores. The effort is aimed at helping SoC designers better optimize the graphics blocks around power consumption, performance and area.
The company gave no specifics on its plans. However, more details may emerge at a TSMC event here this week, focused on the Taiwan foundry’s move into 20 nm and 3-D stacking technologies.
Imagination is working with EDA tool and library developers as well as foundries to help optimize the physical layout of its GPUs. However, the company currently has no plans to sell hardened macros.
New capabilities will span a broad range of chip design areas including standard cell libraries, voltage scaling in process nodes and clock-tree optimization, Tony King-Smith, vice president of marketing at Imagination, said here the day before the opening of the TSMC event. “People are asking us to do more process tuning,” said King-Smith. “We will not deviate from our IP being fully synthesizable, however we will complement it more and more with tuned libraries and tool flows."
“We are making the design more aware of the process with hints in the design database itself--most library vendors with an open mind will be talking with us,” King-Smith added.
Hard macros are rarely used because “no one has the same [chip] floor plan, so it’s better to tune up the flows and libraries so people can harden the designs themselves more effectively,” he added.
The extent of improvements in reduced power consumption, area or increased performance will vary greatly among design teams, depending on the time they put into the optimizations, he said, declining to provide any hard figures.
Foundries as well as SoC designers are driving the demand for more optimization, he said. Most of the effort is now going on at the 28-nm node, but programs have started at 20- and 14/16-nm nodes using FinFETs, he added.
“The foundries are coming to us when characterizing 28- or 20-nm nodes looking for reference designs for what will push their processes,” said King-Smith. “Historically, it has been memory and processors [in that role but] now GPUs are consuming the most area and power on the chip,” he said.
Imagination’s Series 6 graphics cores will be the first to benefit from the optimizations, King-Smith said. Imagination and multiple of its SoC customers now have sample designs using Series 6 cores running in the lab, he added.
So it turns out ARM has been doing this kind of process custo9mization for its CPUs via something it calls POPs for sometime.
Recently ARM started doing this with its Mali graphics cores.
Good context for Imagination's somewhat vague talk of similar ideas.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.