Breaking News
News & Analysis

TSMC taps ARM's V8 on road to 16 nm FinFET

ARM hints at 16-nm V8 chips in 2015
10/16/2012 09:21 PM EDT
14 comments
NO RATINGS
< Previous Page 2 / 2
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
de_la_rosa
User Rank
Rookie
re: TSMC taps ARM's V8 on road to 16 nm FinFET
de_la_rosa   10/20/2012 9:06:39 PM
NO RATINGS
maybe the last presentation we will see from a big player. Beyond 14nm node, is impossible. Unless electron-beam lithography has something under their sleeve?

marcos83
User Rank
Rookie
re: TSMC taps ARM's V8 on road to 16 nm FinFET
marcos83   10/19/2012 11:42:34 AM
NO RATINGS
I think this industry is stalling due to the limitations of resolution. The big players have relied on Moore's law as the backbone of their road-map.

chipmonk0
User Rank
CEO
re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/18/2012 4:04:26 PM
NO RATINGS
Thx

double-o-nothing
User Rank
Rookie
re: TSMC taps ARM's V8 on road to 16 nm FinFET
double-o-nothing   10/18/2012 3:58:51 PM
NO RATINGS
Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure. ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.

rick merritt
User Rank
Blogger
re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:17:55 AM
NO RATINGS
Oh, and the TSVs are supposed to provide much greater bandwidth than today's wire bonded stacks

rick merritt
User Rank
Blogger
re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:17:16 AM
NO RATINGS
They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.

rick merritt
User Rank
Blogger
re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:15:41 AM
NO RATINGS
Intel's Mark Bohr has already said he is considering quad patterning immersion at 10nm. See http://www.eetimes.com/electronics-news/4396146/Intel-sees-quad-patterned-path-to-10-nm-chips

resistion
User Rank
Manager
re: TSMC taps ARM's V8 on road to 16 nm FinFET
resistion   10/17/2012 10:36:45 PM
NO RATINGS
With a wavelength of 13.5 nm and NA of 0.33, 10 nm corresponds to k1 less than 0.25, so indeed the current NXE:3300 won't be useful for very long.

resistion
User Rank
Manager
re: TSMC taps ARM's V8 on road to 16 nm FinFET
resistion   10/17/2012 9:48:15 PM
NO RATINGS
Worse yet, at least some expect 10 nm may require double patterning even for EUV. http://semimd.com/blog/2012/09/17/will-euv-miss-another-node/ And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options. http://semimd.com/blog/2012/10/17/asml-to-acquire-cymer/

chipmonk0
User Rank
CEO
re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/17/2012 3:49:17 PM
NO RATINGS
Rick : Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ? Thx

Page 1 / 2   >   >>
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Top Comments of the Week