The folks from Aldec say that they will be presenting a paper on Platform Validation at Verification Futures 2012 in Windsor, United Kingdom, on Monday 19 November. Platform Validation is at the heart of SoC hardware and software co-verification, and currently one of the EDA industry’s hottest topics.
With technology trends, such as embedded processors, and time-to-market pressures, concurrent engineering demands that software engineers have early access to silicon. Platform Validation extends beyond the realms of hardware design simulation and functional verification (for which Aldec is perhaps best known) and pushes into system hardware and software co-verification.
Jacek Majkowski, Senior Hardware Engineer with Aldec will be presenting the Platform Validation paper and comments: “Whilst embedded system complexity is growing very fast, driven by high customer expectations, verification tools need to keep pace by providing hardware-based methodologies for SoC designers. The complexity grows in both setup of the design under test and the runtime stage of the test. With Aldec’s new HES-7 platform, setup of the high capacity designs is far simpler with the ability to scale the available capacity of the tool, while Standard Co-Emulation Modeling Interface (SCE-MI) interface provides an efficient and standardized way to test the design on an emulation platform.”
Importantly, Aldec provides simulator and hardware boards with software that automates (design) mapping to FPGAs. In addition, thanks to Universal Verification Methodology (UVM), SCE-MI methodologies and supporting hardware/interfaces, it is possible to move freely between hardware simulation, emulation and system prototyping.
Moreover, Aldec’s HES-7 boards can be used in different configurations at different phases of a project. For example, four boards (with two Xilinx Virtex-7 All Programmable FPGAs each) could be used by four engineers (hardware or software) as desktop prototyping platforms; to work on separate parts of the design. Moving toward system integration, a backplane can be used to connect the four HES-7 boards together; delivering the equivalent of 96 million ASIC gates.
Majkowski’s presentation will cover an overview on transaction-based verification technologies, including SCE-MI macro-based and Direct Programming Interface (DPI) function-based synthesizable transactors, eliminating communication bottlenecks that could compromise the performance of hardware emulation systems. Real-life use cases will be shown, as well as two detailed customer case studies on transaction-based verification of large ASICs.
Now in its second year, Verification Futures is organized and run by test and verification services company TVS and the Electronic Chips & Systems design Initiative (ECSI). Engineers wishing to register to attend Verification Futures 2012 in Windsor on 19 November can do so by Clicking Here.
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