SAN JOSE, Calif. – Texas Instruments will extend ARM into what it calls “purpose-built severs” as well as networking gear with a new set of six 28 nm SoCs. The Keystone chips use a mix of ARM Cortex A15 and TI C66x DSPs along with TI security and networking blocks.
“We think the real opportunity for us is to offload some of the processing general purpose servers do,” said Tom Flanagan, director of technical strategy for TI’s multicore processors. “In some cases people may use ARM cores for classic server apps, but that’s not our main target,” said Flanagan.
TI hopes to win sockets in systems designed to handle media processing, video analytics, industrial imaging and control and other high performance computing jobs suitable for its DSPs.
The new chips mark the first time TI has gone after routers and switches in a focused way. It faces a broad set of competitors including Cavium, Freescale and LSI who are also creating SoCs with ARM cores and with their own homegrown accelerators.
“OEMs are looking to move anything they can into a more open environment so they are pretty attracted to ARM cores,” Flanagan said.
TI differentiates its parts in several ways. It uses a 256-bit interface from the cores to the SoC clocked at the full 1.4 GHz data rate of the cores. Several vendors use 128-bit interfaces clocked at a third to half the core rate.
In addition, TI packs as much as 18 Mbytes of aggregate memory on its high-end SoCs. The company claims it is also unique in supporting 1 and 10 Gbit Ethernet MACs in its chips.
At this stage, TI is not saying much about its road map for the SoCs. “We’re looking at 64-bit cores,” he said.
The maximum performance per Watt of the 64-bit ARM A53 core is “more philosophically in line with what like to do,” he said. But TI is still “doing the math” about how it will compare with the A57 and whether 28 or 20 nm process technologies will be the best target.
“The 64-bit ARM cores are not widely available until 2014, so we have time on this,” he added.
Meanwhile, the new Keystone chips sample in December in versions consuming from 6 to 13W. High-end versions use up to four A15s and six C66x DSPs to deliver up to 352 GMACs and 19,600 Dhrystone MIPS.
Two of the chips will use just one DSP core for workloads with less heavy signal-crunching requirements. Two low-end parts will not contain any DSPs and will focus on jobs such as networking and industrial sensor nets.
Prices start at $30 in thousands for chips clocked at 850 MHz. The high-end members of the new family are sampling now with volume production before June. Middle and low-end versions will sample in the second half of 2013.
If I recall correctly the original announcement saying these were to be used as coprocessors for basestations. What changed? Are the chips different, or is it mostly a change in marketing focus? Is this related to the divestiture of the mobile/wireless OMAP
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.