SANTA CLARA, Calif. – Huawei will package an FPGA and a Wide I/O memory on a 2.5-D silicon interposer to bust through memory bandwidth limits in communications systems. The technology presents thorny challenges but could become critical in networking, said a senior scientist for Huawei.
The new device, in the works only about three months, will significantly reduce board space while increasing performance. “2.5D silicon interposers seem to be the best fit for networking companies—in fact, they are mission critical,” said Anwar A. Mohammed, a senior staff scientist for packaging working in Huawei’s U.S. R&D center here.
A year ago, Xilinx announced its most dense FPGA to date using multiple die side-by-side on a 2-5-D silicon interposer. At that time Xilinx talked about great interest in the technology from networking companies and about plans for future products that combined FPGAs and memories.
Huawei spent more than a year evaluating as many as nine approaches before selecting the 2.5-D silicon interposer. Huawei is working with Altera, Tezzaron, eSilicon and Singapore’s Institute of Microelectronics on the project (described below).
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The new 2.5-D device will replace ten to twenty DDR memories and an ASIC used in current Huawei systems, saving nearly 18 percent in board space and tripling bandwidth per Watt. The Wide IO component will support eight 128-bit channels, and the FPGA will include Huawei logic, a PCI Express block, and at least three 3 Gbit/s serdes links.
“The size of our line cards is constant but you want to put more and more functions into it, so 2.5-D is a powerful tool for that,” said Mohammed in a keynote address here
. “There’s a potential for cost reduction as we combine more functions into it, even though initially it will be more expensive,” he said.
Comms companies have relied on ever faster serdes to speed data to memory, but serdes gains are coming more slowly with the latest process technologies. “The old solution is not working anymore,” said Mohammed.
Huawei and partners still have plenty of challenges to resolve to make their 2.5-D design viable. Silicon interposers are still relatively expensive, and lower cost glass and organic options are not yet ready for use. Engineers lack known good die, 2.5-D CAD tools, enough reliability data, as well as strategies for test, rework and thermal management.
In addition the 2.5-D supply chain is still immature and lacks options. Return on investment calculations are still unclear, too.
“There are many unknowns, so it will not be completely surprising if this does not succeed,” said Mohammed, who called for more pre-competitive research. “Let’s share ideas to make sure the technology succeeds,” he said.
The 2.5-D approach is seen as an interim step to full 3-D stacks of
chips linked with through silicon vias. Just two weeks ago one analyst
speculated a decline in Altera's finanical results was due to a
reduction in FPGA designs from Huawei.Related stories:
Xilinx Pioneers Uncertain Future for Chip Stacking2.5D ICs are more than a stepping stone to 3D ICs
3D-IC Design: The Challenges of 2.5D versus 3D