SAN JOSE, Calif. – Panasonic with show a 60 GHz chip set, Ericsson will bring carrier aggregation to LTE and Finisar and Hitachi will show building blocks for 25 Gbit/second wired links at the International Solid-State Circuits Conference in February. The devices push the limits of today’s Wi-Fi, 4G cellular and Ethernet networks.
Panasonic will describe a 60 GHz chip set supporting the WiGig and IEEE 802.11ad standards capable of supporting 1.5 Gbits/second data rates at distances of one meter. The part will drive 1.8 Gbits/second throughput at the level of the media access controller while consuming 788 mW in transmit and 984 mW in receive mode.
The set includes an RF chip and separate digital baseband made in 90 and 40 nm CMOS processes, respectively. It is one of at least five chips now in production for 60 GHz standards by companies including startup Wilocity, according to the WiGig Alliance.
Panasonic was one of the early partners of the WirelessHD effort of startup SiBeam, now part of Silicon Image. The group was early to promote 60 GHz chips for wireless links between set-tops and flat-screen displays.
Separately, Ericsson will detail a single-chip 4G cellular receiver that supports use of non-contiguous spectrum bands. The so-called carrier aggregation feature is an important element of the Release 10 version of LTE that carriers such as T-Mobile will adopt next year to help them achieve broadband links despite a lack of wide spectrum bands.
The Ericsson chip can receive up to three 20MHz LTE carriers simultaneously. It consumes 155mW and 435mW when receiving one and three carriers, respectively, and is made in a 65 nm process.
In addition, Finisar and Hitachi will describe building blocks for 25 Gbit/s wired links. The faster channels will help create more efficient 100 Gbit/s Ethernet links for carriers’ core networks that currently use ten 10G channels.
Finisar will show a quad 25G transimpedance amplifer made in 130 nm silicon germanium BiCMOS, dissipating 83 mA from a 3.3 V supply. Hitachi will show a full four-channel 25G CMOS optical receiver with a -9.7dBm sensitivity.
Separately, Broadcom will detail at ISSCC a 40 Gbit/s CMOS chipset for core networks.