“It could be part of Project Denver or a technology to connect multiple
GPUs together for Tesla-based supercomputer support,” said Krewell of
Linley Group. “I haven't heard any details of how Project Denver is
proceeding, but Nvidia certainly needs to develop high performance
interfaces that can connect arrays of Project Denver heterogeneous
Nvidia’s graphics chips are already widely used in
massive clusters for supercomputers, including the world’s current
fastest system called Titan.
Separately, China’s Institute of
Computing Technology will describe a new version of the Godson 3B
processor made using a 32-nm process. Previously ICT showed eight-core
65-nm CPUs and suggested it would leapfrog to 28-nm designs.
ISSCC, engineers will detail Godson-3B1500, a 32-nm high-K, metal gate
part delivering 172.8 Gflops when running at 1.35 GHz at 40 W. That’s up
from 128 Gflops for the 65-nm version also drawing 40 W, thanks to the
new process as well as architecture and circuit enhancements.
other papers, Texas Instruments and MIT will describe a 200-MHz video
decoder implementing the High-Efficiency Video Coding draft standard to
deliver 249 Mpixels/s. It enables 3840 x 2160 pixel resolution while
consuming 76 mW at 0.9 V.
Renesas will describe a 28-nm
integrated handset SoC with a dual-core 1.5 GHz CPU, an LTE/HSPA+
baseband modem processor, graphics accelerators and a power management
unit. AMD, IBM and Oracle will present papers on their Jaguar, zSeries
and Sparc T5 processors already described in August at Hot Chips.