HP Labs continues to conduct
experiments on the nanostore concept with promising results. But
Ranganathan declined to provide any specifics, noting the work is still
as much as three years from commercial products.
devices could ride a confluence of multiple waves of change. “The
technology changes and workloads inflections ahead are incredibly
interesting for system design,” he said.
In computing, he noted
processors made a “sharp right turn” in about 2005 when performance
gains for single core processors plateaued and multicore architectures
In storage, disk drive capacity has outpaced data
access times. DRAM capacity growth has taken a “soft right turn” from
traditional levels of 60 percent a year to about 25 percent a year, he
The rise of server SoCs and eventually 3-D stacks along
with flash memory in server designs could help breakthrough such
bottlenecks. The changes come about the same time that networking is
shifting more deeply from copper to optical links.
data growth is far outpacing Moore’s Law, driving new workloads. The
researcher noted a “growing complexity and dynamism of data access.”
Today’s searches increasingly involve accessing multiple real-time and
static databases as well as overlaid sources of personal and contextual
“Compared to a simple click, which once was just to a
single Web server, we now have very sophisticated data analysis from
multiple repositories with complex cross correlations,” he said. “It’s
big data, but it’s also fast data from multiple streams with deep
analytics." Related stories:
@bobdvb: It's unclear because they haven't said much about the lo0gic part of the device.
Many researchers including some at Stanford and Berkeley have talked about kinds of smart memories before. HP's unique angle is using its memristor as the memory.
Turns out there are many logic blocks each suited for different jobs that HP Labs is exploring adding to memristors.
The idea is to invert the old idea of a memory hierarchy serving processors. Instead memory is central and there is a hierarchy (or taxonomy) of processing done on it.
It will be great if something useful comes from HP's nanostore and 3D stacking crossbars. However, I would have more respect for the researchers involved if they stood on the merit of their own R&D rather than continuing to use Chua's "memristor" as a PR gimmick.
It is really astonishing that HP’s Labs still believe in their “memristor” stuff.
Non-volatile memristive systems are conceptually defined by a set of characteristic mathematical equations. Thus, solid state memory devices should only be labeled "memristors" if they operate physically in accordance with this mathematical framework. However, up to now no one has been able to propose a reasonable physical model that satisfies these equations, although there are some claims appearing in scientific literature. Even HP Labs have not invented or found a device which works like a genuine, non-volatile memristive system. Their fabled memristor model which was presented in the “NATURE” paper “The missing memristor found” (Nature 453, 80-83 (2008)) suffers from severe flaws in its construction. This can be easily shown by analyzing the model under aspects of textbook electrochemistry.
What is termed "memristors" by HP are memory devices based on "resistance switching" effects. Resistance switching behavior is often observed on specific metal/insulator/metal structures after a soft-breakdown of the insulating material has occurred (electroforming step). These phenomena are well known since decades and are in no way related to the concept of memristor/memristive systems. Soft-breakdown can induce highly defective, filament-like structures somewhere in the insulating matrix which are susceptible to external interferences. Probably, most resistance switching effects result from localized chemical/physical phase transformations in these regions due to, for example, local heating or high-field electrolytic processes triggered by means of electric stressing. Localized effects at the nanoscale involve a lot of reliability and stability issues. SK Hynix and other companies seem to be aware of these problems.
So, what is the real intention behind all these “memristor” stories? HP is doing no favors to itself announcing time and again such “breaking” news.
I believe A.Sceptic's issue is not with "Hynix and other companies" but rather with those who write memristor papers and are either not aware of the physics issues or have made no real attempt to incorporate the actual physics into dynamic systems models (regardless of whether it is called a "memristor" or not).
The lead HP memristor scientist (Stan Williams) has publically stated in an earlier EETimes article that HP's memristor research is "essentially complete" and any delay is for business reasons blamed on Hynix. However, to my knowledge, there is no realistic model from HP or anyone else incorporating the known physics into a dynamic systems model (regardless of whether you call it a memristor or not). The lack of accurate physics models will make product design difficult and Hynix's engineers will likely need to rely on trial and error for manufacture. This will likely make it more costly and time consuming to manufacture "memristors".
The memristor terminology is probably for PR. Defects, especially charge trapping type, lend themselves to memory effects pretty easily, and nothing is ever defect free, so a lot of these defect-driven memories can appear under the right stress conditions.
Charge trapping models for resistance switching would be open to objections which apply to all models which do not involve stable atomic/ionic rearrangements, i.e., phase changes, in localized regions of the considered materials: the memory states last for several years without decay, and it is hard to see that non-equilibrium charge distributions could exist for so long in thin-film devices.