Ultimately, said Bohr, the distinction between regular processors and SoCs is blurring, with even CPUs like Ivy Bridge incorporating typical SoC elements like multiple computing cores, graphics, high performance IO circuits and cache. SoC,s however, are still taking those components to the extreme. “It’s a matter of degree,” Bohr said.
Indeed, Intel’s SoC is almost identical to its CPU version in terms of structure, including only some “minor tweaking” to provide either the lower leakage or higher volatage. It could even be described as a “superset” of the CPU version with expanded features.
The SoC and CPU versions share many of the same process features; the same transistor structure and pitch along with similar interconnect and fab process equipment. “These two technologies can be run side by side in the same factory,” said Bohr, noting that all the yield learning for Ivy Bridge had been translatable.
Bohr acknowledged that SoCs had presented Intel with new challenges. “When you talk about leakage, once you get down into the below 30 pico amp range, you have to deal with multiple sources of leakage, whether it’s through the gate oxide or leakage from source to drain or leakage from the drain to the substrate,” he said, adding that it had taken a lot of “tweaking an balancing” to finally get it right.
The turning point had finally been reached, he said, with the firm’s 32-nm Medfield SoC. “You’ll see some pretty impressive SoC products coming next year on the 22nm generation,” he said.
In terms of how Intel’s 22-nm SoC process stacks up against the 28-nm low power or forthcoming 20-nm processes from TSMC, Bohr claimed Intel had “far surpassed” the performance and low leakage capabilities of competitors. “We have a significant lead over our competitors,” he asserted.
Intel is also banking on he new technology process having a long tail. “We know that it’s scalable to 14-nm,” he said, concluding that tri-gate was not only a big power advantage for Intel’s CPUs, but for other low power SoCs.
TSMC has an infrastructure and process to enable IP houses to develop analog, memory and other process-specific IP. That way anyone who uses the new process can choose from many offering. That's my understanding why Intel's mobile offerings are so poor-featured compared ARM-based developed by Qualcomm, Samsung and Nvidia. Tri-gate process is a great improvement and the step in the right direction to enable mobile market, but I am not sure if this is sufficient alone. Even if Intel opens its fab to others today, it still has a lot to catch up with the way other fabs are supporting their customers. Thanks for the interesting article!
Everyone who plays/played the "Master of Orion" or the "Civilization" series of global/galactic strategy games knows that "raping the tech tree" is the key to victory. I can't see how that's any different for the semiconductor industry and the process technology tree.
This looks like (at least) a dual gate oxide SoC, so it's definitely more expensive to make than single gate oxide logic. Triple gate oxide is not unheard of either. The gate layer in this case is therefore already triple patterned for non-lithographic, electrical reasons alone.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.