SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22-nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here Monday (Dec. 10). Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.
IBM said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm node. Intel retains an edge with several 22-nm chips already in volume production, and disclosure at IEDM of a variant of the process for SoCs for a wide range of applications.
The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” Mark Bohr, head of Intel’s process technology development group, said in a brief interview. The process is geared for a much wider array of designs than that of IBM, he added.
Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.
Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.
“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.
Separately, Bohr said Intel does have a growing foundry business that may include some higher volume applications than its current announced customers like FPGA startup Achronix. However, “we don’t intend to be in the general-purpose foundry business…[and] I don’t think the [foundry] volumes ever will be huge” for Intel, he said.
Search web for TSMC & Intel wafer output.
2011 TSMC states 12,970,000 300 millimeter wafers are 1.5 times more than Intel or 8,646,667.
Searched for Intel 3rd party estimate, time was passing, stated TSMC.
TSMC 2011 Gross Revenue 14,540,000,000 / 12,970,000 = $498.24
TSMC 2011 Net Revenue $5,100,000,000 / 12,970,000 = $175
Intel 2011 Gross Revenue $59,999,000,000 / 8,646,667 = $6,936
Intel 2011 Net Revenue $12,942,000,000 / 8,646,667 = $1,497
Intel Gross Revenue per Wafer is 14x TSMC
Intel Net Revenue per Wafer is 3x TSMC
But no this is not what I meant by Intel cooking the books.
Most blatant is misrepresentation that annual cooperative advertising expense is marketing cost 1993 to 2011 totaling $29,786,000,000. That marketing cost is actually a combination of IDM customer’s rebated fee accruals known as Intel Inside tied charge back metered price discrimination and sales rewards for loyalty.
In tied charge back form total sum is a kick through paid by PC IDMs taken as rebated fee accrual by Intel on sales price passed through by Intel to sales agents for channel stocks movement reporting. As marketing kick back to sales agents is cost at 5.15% of in system processor price stuck to PC end buyer as hidden charge in sales invoice.
Another irregularity for economists, financiers, investors, competitors, customers is calculating extended Intel story problems that are processor shipment leaks through Intel and press sources for determining revenues and margins quarters into future time.
This form of RICO known as collusion by model places Intel gross revenue higher than Intel stated, appears to over report data center revenue and under report PC client group revenue.
Alternatively QUANTA higher revenue difference can be sign of poor yield, unsold inventory, unreported revenues concealing unreported cost centers, to offset product priced less than cost, employee and stakeholder theft.
How do you mean Intel is cooking the books? Are you suggesting their GM is higher than it appears? I remember reading an EET article saying their costs per wafer are three times as high as TSMC.
I agree with 3D guy for Intel standard merchant product. Where SOCs do present another question including for Intel.
For any standard product short run through five quarters of production requires a very volume high peak to see a marginal cost reduction for pulling down the full run average. Foundries may not be as product focused on the line. And how many see greater than 100 million unit runs?
On QUANTA for determining Intel marginal cost of production jury is still out on whether there actually is a cost reduction per millimeter square of dice area from Sandy Bridge to Ivy Bridge. Increased Ivy dice suggest there should be on Intel’s standard integration rule of no more than 10% increase in wafer cost per generation, although that rule has been broken many times in the past. Then the question arises whether or not there will actually be demand for that volume of Ivy supply? Also knowing Sandy oversupplied still floods the channels.
Ivy frequency distribution suggests Intel is fibbing on the ease of manufacturing trigate and this analysts suspects work overtime to make the sort above 2.4 GHz.
Finally having accelerated at 32 nanometer from a commercial industrial art into 22 nanometers applied science what are the real RISK development costs over production alone which this analyst suggests are high.
Intel annual financial won’t necessarily reveal the whole story where the books have been substantially cooked for a very long time. With a new generation of Haswell product in the mix, this analyst believes RISK production costs are more likely to rise than stay flat or decline.
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